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PIC24F04KA201 Family Data Sheet
14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLPTM Technology
(c) 2009 Microchip Technology Inc.
Preliminary
DS39937B
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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(c) 2009 Microchip Technology Inc.
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14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLPTM Technology
Power Management Modes:
* * * * * * * * * Run - CPU, Flash, SRAM and Peripherals On Doze - CPU Clock Runs Slower than Peripherals Idle - CPU Off, Flash, SRAM and Peripherals On Sleep - CPU, Flash and Peripherals Off and SRAM On Deep Sleep - CPU, Flash, SRAM and Most Peripherals Off Run mode Currents Down to 8 A Typical Idle mode Currents Down to 2 A Typical Deep Sleep mode Currents Down to 20 nA Typical Watchdog Timer 350 nA, 1.8V Typical
Analog Features:
* 10-Bit, up to 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle * Dual Analog Comparators with Programmable Input/ Output Configuration * Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Compatible with mTouchTM capacitive sensing - Time measurement, down to 1 ns resolution - Delay/pulse generation, down to 1 ns resolution
High-Performance CPU:
* Modified Harvard Architecture * Up to 16 MIPS Operation @ 32 MHz * 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options * 17-Bit by 17-Bit Single-Cycle Hardware Multiplier * 32-Bit by 16-Bit Hardware Divider * 16-Bit x 16-Bit Working Register Array * C Compiler Optimized Instruction Set Architecture
Special Microcontroller Features:
* Operating Voltage Range of 1.8V to 3.6V * High-Current Sink/Source (18 mA/18 mA) on All I/O Pins * Flash Program Memory: - Erase/write cycles: 10000 minimum - 40 years data retention minimum * Fail-Safe Clock Monitor * System Frequency Range Declaration bits: - Declaring the frequency range helps in optimizing the current consumption. * Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation * In-Circuit Serial ProgrammingTM (ICSPTM) * Programmable High/Low-Voltage Detect (HLVD) * Brown-out Reset (BOR): - Standard BOR with three programmable trip points; can be disabled in Sleep * Extreme Low-Power DSBOR for Deep Sleep, LPBOR for all other modes
Peripheral Features:
* Serial Communication modules: - SPI, I2CTM and UART modules * Three 16-Bit Timers/Counters with Programmable Prescaler * 16-Bit Capture Inputs * 16-Bit Compare/PWM Output * Configurable Open-Drain Outputs on Digital I/O Pins * Up to Three External Interrupt Sources
Comparators
04KA200 04KA201
14 20
4K 4K
512 512
3 3
1 1
1 1
1 1
SPI
PIC24F Device
1 1
1 1
7 9
2 2
(c) 2009 Microchip Technology Inc.
Preliminary
DS39937B-page 1
CTMU (ch) 7 9
10-Bit A/D (ch)
Output Compare/ PWM
Program Memory (bytes)
Input Capture
SRAM (bytes)
Timers 16-Bit
UART/ IrDA(R)
I2CTM
Pins
PIC24F04KA201 FAMILY
Pin Diagrams
14-Pin PDIP, TSSOP(1)
MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 PGD3/SOSCI/AN2/C2INB/HLVDIN/CN1/RB4 PGC3/SOSCO/AN3/C2INA/T1CK/CN0/RA4
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD VSS REFO/U1RX/SS1/T2CK/T3CK/INT0/CTPLS/CN11/RB15 AN10/CVREF/U1TX/SDI1/OCFA/C1OUT/INT1/CTED2/CN12/RB14 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 SDA1/U1BCLK/U1RTS/SDO1/CN21/RB9 SCL1/U1CTS/SCK1/CN22/RB8
PIC24F04KA200
20-Pin PDIP, SSOP, SOIC(1)
MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 U1RX/CN6/RB2 OSCI/CLKI/AN4/C1INB/CN30/RA2 OSCO/CLKO/AN5/C1INA/CN29/RA3 PGD3/SOSCI/CN1/RB4 PGC3/SOSCO/T1CK/CN0/RA4
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 SDA1/U1BCLK/U1RTS/CN21/RB9 SCL1/U1CTS/CN22/RB8 U1TX/INT0/CN23/RB7
Note 1:
All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
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Preliminary
PIC24F04KA201
(c) 2009 Microchip Technology Inc.
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Pin Diagrams (Continued)
20-Pin QFN(1,2)
PGD2/AN1/VREF-/CN3/RA1 PGC2/AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD VSS
20 19 18 17 16 15 1 14 2 U1RX/U1BCLK/CN6/RB2 3 PIC24F04KA201 13 OSCI/CLKI/AN4/C1INB/CN30/RA2 4 12 OSCO/CLKO/AN5/C1INA/CN29/RA3 5 11 6 7 8 9 10
PGD3/SOSCI/CN1/RB4 PGC3/SOSCO/T1CK/CN0/RA4 U1TX/INT0/CN23/RB7 SCL1/U1CTS/CN22/RB8 SDA1/U1BCLK/U1RTS/CN21/RB9 AN2/C2INB/CN4/RB0 AN3/C2INA/CN5/RB1 REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6
Note 1: 2:
Connecting the bottom pad to Vss is recommended. All device pins have a maximum voltage of 3.6V and are not 5V tolerant.
(c) 2009 Microchip Technology Inc.
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Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 15 3.0 CPU ........................................................................................................................................................................................... 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory .............................................................................................................................................................. 43 6.0 Resets ........................................................................................................................................................................................ 51 7.0 Interrupt Controller ..................................................................................................................................................................... 57 8.0 Oscillator Configuration .............................................................................................................................................................. 81 9.0 Power-Saving Features .............................................................................................................................................................. 91 10.0 I/O Ports ..................................................................................................................................................................................... 99 11.0 Timer1 ..................................................................................................................................................................................... 101 12.0 Timer2/3 ................................................................................................................................................................................... 103 13.0 Input Capture............................................................................................................................................................................ 109 14.0 Output Compare ....................................................................................................................................................................... 111 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 117 16.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 125 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 133 18.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 141 19.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 143 20.0 Comparator Module.................................................................................................................................................................. 153 21.0 Comparator Voltage Reference................................................................................................................................................ 157 22.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 159 23.0 Special Features ...................................................................................................................................................................... 163 24.0 Development Support............................................................................................................................................................... 173 25.0 Instruction Set Summary .......................................................................................................................................................... 177 26.0 Electrical Characteristics .......................................................................................................................................................... 185 27.0 Packaging Information.............................................................................................................................................................. 205 Appendix A: Revision History............................................................................................................................................................. 213 Index .................................................................................................................................................................................................. 215 The Microchip Web Site ..................................................................................................................................................................... 219 Customer Change Notification Service .............................................................................................................................................. 219 Customer Support .............................................................................................................................................................................. 219 Reader Response .............................................................................................................................................................................. 220 Product Identification System............................................................................................................................................................. 221
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(c) 2009 Microchip Technology Inc.
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TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
(c) 2009 Microchip Technology Inc.
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NOTES:
DS39937B-page 6
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(c) 2009 Microchip Technology Inc.
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1.0 DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information for the following devices:
* PIC24F04KA200 * PIC24F04KA201
The PIC24F04KA200 and PIC24F04KA201 devices incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing users to incorporate power-saving ideas into their software designs. * Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. * Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: - Idle Mode: The core is shut down while leaving the peripherals active. - Sleep Mode: The core and peripherals that require the system clock are shut down, leaving the peripherals that use their own clock, or the clock from other devices, active. - Deep Sleep Mode: The core, peripherals (except DSWDT), Flash and SRAM are shut down.
The PIC24F04KA201 family introduces a new line of extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. It also offers a new migration option for those high-performance applications, which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a digital signal processor.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC(R) digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: * 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces * Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) * A 16-element working register array with built-in software stack support * A 17 x 17 hardware multiplier with support for integer math * Hardware support for 32-bit by 16-bit division * An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as C * Operational performance up to 16 MIPS
1.1.3
OSCILLATOR OPTIONS AND FEATURES
The PIC24F04KA201 family offers five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-2 clock output. * Two fast internal oscillators (FRCs): One with a nominal 8 MHz output and the other with nominal 500 kHz output. These outputs can also be divided under software control to provide clock speed as low as 31 kHz or 2 kHz. * A Phase Locked Loop (PLL) frequency multiplier, available to the External Oscillator modes and the 8 MHz FRC oscillator, which allows clock speeds of up to 32 MHz. * A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.
(c) 2009 Microchip Technology Inc.
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PIC24F04KA201 FAMILY
The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
1.3
Details on Individual Family Members
Devices in the PIC24F04KA201 family are available in 14-pin and 20-pin packages. The general block diagram for all devices is displayed in Figure 1-1. The devices are different from each other in two ways: 1. 2. Number of ADC channels (9 channels on 20-pin parts, 7 channels on 14-pin parts). Available I/O pins and ports (12 pins on two ports for 14-pin devices and 18 pins on two ports for 20-pin devices).
1.1.4
EASY MIGRATION
Regardless of the memory size, all the devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also helps in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 14-pin to 20-pin devices. The PIC24F16KA102 family is directly compatible for migration to larger program and data memory. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex.
All other features for devices in this family are identical; these are summarized in Table 1-1. A list of the pin features available on the PIC24F04KA201 family devices, sorted by function, is provided in Table 1-2. Note: Table 1-1 provides the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams on pages 2 and 3 of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
1.2
Other Special Features 1.4
* Communications: The PIC24F04KA201 family incorporates a range of serial communication peripherals to handle a range of application requirements. There is an I2CTM module that supports both the Master and Slave modes of operation. It also comprises a UART with built-in IrDA(R) encoders/decoders and an SPI module. * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speed. The 16-deep result buffer can be used either in Sleep to reduce power, or in Active mode to improve throughput. * Charge Time Measurement Unit (CTMU) Interface: The PIC24F04KA201 family includes the new CTMU interface module, which can be used for capacitive touch sensing using Microchip's mTouchTM technology, proximity sensing and also for precision time measurement and pulse generation.
Differences from PIC24F16KA102 Family
The PIC24F04KA201 family architecture is very similar to that of the PIC24F16KA102 family. The PIC24F04KA201 family is a subset of the PIC24F16KA102 devices. The PIC24F16KA102 additional features: * * * * * family has the following
Larger Program Memory Larger Data Memory CRC Module Debugging Capabilities through ICSPTM Additional I/O on 20-Pin Devices (up to 24 I/O pins) * Data EEPROM memory * Boot Segment and General Segments for Program Code (with available code protection) * One Additional UART (2 total)
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(c) 2009 Microchip Technology Inc.
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TABLE 1-1: DEVICE FEATURES FOR THE PIC24F04KA201 FAMILY
PIC24F04KA200 PIC24F04KA201 DC - 32 MHz 4K 1408 512 25 (21/4) PORTA<6:0> PORTB<15:14, 9:8, 4> 12 3 1 1 1 11 1 1 1 7 2 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 14-Pin PDIP/TSSOP 20-Pin PDIP/SSOP/SOIC/QFN 9 17 PORTA<6:0> PORTB<15:12, 9:7, 4, 2:0> 18
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Features
Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays)
Instruction Set Packages
(c) 2009 Microchip Technology Inc.
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FIGURE 1-1: PIC24F04KA201 FAMILY GENERAL BLOCK DIAGRAM
Interrupt Controller 8 PSV and Table Data Access Control Block 16
Data Bus 16 16 Data Latch
23
PCH PCL Program Counter Repeat Stack Control Control Logic Logic
Data RAM Address Latch 16 16 Read AGU Write AGU PORTA(1) RA<6:0>
23 Address Latch Program Memory Data Latch
PORTB(1) RB<15:12, 9:7> RB<4, 2:0>
Address Bus 24 Inst Latch Inst Register Instruction Decode and Control Control Signals Timing OSCO/CLKO OSCI/CLKI Generation FRC/LPRC Oscillators Power-up Timer
Start-up Timer
EA MUX Literal Data 16 16
16
Divide Support 17x17 Multiplier
16 x 16 W Reg Array
Oscillator
Power-on Reset Watchdog Timer DSWDT
16-Bit ALU 16
Precision Band Gap Reference
BOR
VSS VDD, HLVD
MCLR Timer1 Timer2/3 CTMU 10-Bit ADC Comparators
REFO
IC1
OC1/PWM
CN1-17(1)
SPI1
I2C1
UART1
Note 1:
All pins or features are not implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.
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TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS
Pin Number Function 14-Pin PDIP/TSSOP/ SOIC 2 3 6 7 4 5 11 -- -- 9 5 4 11 7 6 10 4 5 7 6 2 3 -- -- -- 10 12 11 -- -- 9 8 -- 5 4 11 10 11 12 10 12 11 10 20-Pin PDIP/SSOP/ SOIC 2 3 4 5 7 8 17 16 15 13 8 7 17 5 4 14 7 8 10 9 2 3 4 5 6 14 18 17 16 15 13 12 11 8 7 17 14 15 16 14 11 17 14 20-Pin QFN 19 20 1 2 4 5 14 13 12 10 5 4 14 2 1 11 4 5 7 6 19 20 1 2 3 11 15 14 13 12 10 9 8 5 4 14 11 12 13 11 8 14 11 I/O Input Buffer Description
AN0 AN1 AN2 AN3 AN4 AN5 AN10 AN11 AN12 U1BCLK C1INA C1INB C1OUT C2INA C2INB C2OUT CLKI CLKO CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN8 CN11 CN12 CN13 CN14 CN21 CN22 CN23 CN29 CN30 CVREF CTED1 CTED2 CTPLS IC1 INT0 INT1 INT2 Legend:
I I I I I I I I I O I I O I I O I O I I I I I I I I I I I I I I I I I O I I O I I I I
ANA ANA ANA ANA ANA ANA ANA ANA ANA -- ANA ANA -- ANA ANA -- ANA -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ST ST -- ST ST ST ST External Interrupt Inputs Comparator Voltage Reference Output CTMU Trigger Edge Input 1 CTMU Trigger Edge Input 2 CTMU Pulse Output Input Capture 1 Input Interrupt-on-Change Inputs UART1 IrDA(R) Baud Clock Comparator 1 Input A (Positive input) Comparator 1 Input B (Negative input option 1) Comparator 1 Output Comparator 2 Input A (Positive input) Comparator 2 Input B (Negative input option 1) Comparator 2 Output Main Clock Input Connection System Clock Output A/D Analog Inputs
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2CTM = I2C/SMBus input buffer
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TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number Function 14-Pin PDIP/TSSOP/ SOIC 6 1 10 11 4 5 2 3 7 6 2 3 4 5 7 1 10 -- -- -- 6 8 9 -- -- 11 12 12 8 8 9 11 9 6 7 12 7 12 12 8 9 12 11 20-Pin PDIP/SSOP/ SOIC 15 1 14 17 7 8 2 3 10 9 2 3 7 8 10 1 14 4 5 6 9 12 13 15 16 17 18 18 15 12 13 17 16 9 10 18 10 18 18 12 13 6 11 20-Pin QFN 12 18 11 14 4 5 19 20 7 6 19 20 4 5 7 18 11 1 2 3 6 9 10 12 13 14 15 15 12 9 10 14 13 6 7 15 7 15 15 9 10 3 8 I/O Input Buffer Description
HLVDIN MCLR OC1 OCFA OSCI OSCO PGC2 PGD2 PGC3 PGD3 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RB0 RB1 RB2 RB4 RB8 RB9 RB12 RB13 RB14 RB15 REFO SCK1 SCL1 SDA1 SDI1 SDO1 SOSCI SOSCO SS1 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX Legend:
I I O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I O I O I/O I I I I O I O
ANA ST -- -- ANA ANA ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST I2C I2C ST -- ANA ANA ST ST ST ST ST -- ST --
HLVD Voltage Input Master Clear (device Reset) Input Output Compare/PWM Outputs Output Compare Fault A Main Oscillator Input Connection Main Oscillator Output Connection In-Circuit Debugger and ICSP Programming Clock In-Circuit Debugger and ICSP Programming Data In-Circuit Debugger and ICSP Programming Clock In-Circuit Debugger and ICSP Programming Data
PORTA Digital I/O
PORTB Digital I/O
Reference Clock Output SPI1 Serial Clock Input/Output I2C1 Synchronous Serial Clock Input/Output I2C1 Data Input/Output SPI1 Serial Data Input SPI1 Serial Data Output Secondary Oscillator Input Secondary Oscillator Output Slave Select Input/Frame Select Output (SPI1) Timer1 Clock Timer2 Clock Timer3 Clock UART1 Clear to Send Input UART1 Request to Send Output UART1 Receive UART1 Transmit Output
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2CTM = I2C/SMBus input buffer
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TABLE 1-2: PIC24F04KA201 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number Function 14-Pin PDIP/TSSOP/ SOIC 14 1 3 2 13 20-Pin PDIP/SSOP/ SOIC 20 1 3 2 19 20-Pin QFN 17 18 20 19 16 I/O Input Buffer Description
VDD VPP VREFVREF+ VSS Legend:
P P I I P
-- -- ANA ANA --
Positive Supply for Peripheral Digital Logic and I/O Pins Programming Mode Entry Voltage A/D and Comparator Reference Voltage (low) Input A/D and Comparator Reference Voltage (high) Input Ground Reference for Logic and I/O Pin
ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2CTM = I2C/SMBus input buffer
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2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS
Basic Connection Requirements
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
C2(2)
2.1
VDD
VDD
Getting started with the PIC24FXXXX of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") * ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24F devices only) (see Section 2.4 "Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)") These pins must also be connected if they are being used in the end application: * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used.
R1 R2
MCLR
VSS
(1) (1)
(EN/DIS)VREG VCAP/VDDCORE
C1 PIC24FXXXX
VSS VDD
C7
C6(2)
AVDD VDD VSS AVSS VDD VSS
C3(2)
C5(2)
C4(2)
Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 k R2: 100 to 470 Note 1: See Section 2.4 "Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)" for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.
2:
The minimum mandatory connections are shown in Figure 2-1.
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2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
2.3
Master Clear (MCLR) Pin
The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.
The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
VDD R1
EXAMPLE OF MCLR PIN CONNECTIONS
R2 JP C1
MCLR PIC24FXXXX
Note 1:
2.2.2
TANK CAPACITORS
2:
R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F.
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2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)
This section applies only to PIC24F devices with an on-chip voltage regulator.
2.5
ICSP Pins
Note:
The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: * For ENVREG, tie to VDD to enable the regulator or to ground to disable the regulator * For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator When the regulator is enabled, a low-ESR (<5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. A suitable example is the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. The placement of this capacitor should be close to VCAP/VDDCORE. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 26.0 "Electrical Characteristics" for additional information. When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 26.0 "Electrical Characteristics" for information on VDD and VDDCORE.
The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to the MPLAB(R) ICD 2, MPLAB ICD 3 or REAL ICETM emulator. For more information on the ICD 2, ICD 3 and REAL ICE emulator connection requirements, refer to the following documents that are available on the Microchip web site. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" (DS51331) * "Using MPLAB(R) ICD 2" (poster) (DS51265) * "MPLAB(R) ICD 2 Design Advisory" (DS51566) * "Using MPLAB(R) ICD 3" (poster) (DS51765) * "MPLAB(R) ICD 3 Design Advisory" (DS51764) * "MPLAB(R) REAL ICETM In-Circuit Emulator User's Guide" (DS51616) * "Using MPLAB(R) REAL ICETM In-Circuit Emulator" (poster) (DS51749)
FIGURE 2-3:
FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP
10
1 ESR ()
0.1
0.01
0.001
0.01
0.1
1 10 100 Frequency (MHz)
1000 10,000
Note:
Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25C, 0V DC bias.
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2.6 External Oscillator Pins 2.7
Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-4. For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work"
Configuration of Analog and Digital Pins During ICSP Operations
If the MPLAB ICD 2, ICD 3 or REAL ICE emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the A/D pins that are initialized by the MPLAB ICD 2, ICD 3 or REAL ICE emulator must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When the MPLAB ICD 2, ICD 3 or REAL ICE emulator is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic `0', which may affect user application functionality.
2.8
Unused I/Os
FIGURE 2-4:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low.
Main Oscillator 13 Guard Ring Guard Trace Secondary Oscillator 14 15 16 17 18 19 20
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3.0
Note:
CPU
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the "PIC24F Family Reference Manual", Section 2. "CPU" (DS39703).
For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to eight sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is illustrated in Figure 3-1.
The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer (SSP) for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary of program memory defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.
3.1
Programmer's Model
Figure 3-2 displays the programmer's model for the PIC24F. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. Table 3-1 provides a description of each register. All registers associated with the programmer's model are memory mapped.
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FIGURE 3-1:
PSV and Table Data Access Control Block Interrupt Controller 8 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16
PIC24F CPU CORE BLOCK DIAGRAM
23
Address Latch Program Memory Data Latch Address Bus ROM Latch 24
EA MUX
16
16
Instruction Reg
Control Signals to Various Blocks
Hardware Multiplier Divide Support
16 x 16 W Register Array 16
Literal Data 16-Bit ALU 16
Instruction Decode and Control
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register
Register(s) Name W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON
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FIGURE 3-2: PROGRAMMER'S MODEL
15 Divider Working Registers W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers 0
Multiplier Registers
SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL
0 0 0 0
0
0
0 ALU STATUS Register (SR)
-- -- -- -- -- -- -- DC
IPL RA N OV Z C 210
15
0 CPU Control Register (CORCON)
-- -- -- -- -- -- -- -- -- -- -- -- IPL3 PSV -- --
Registers or bits shadowed for PUSH.S and POP.S instructions.
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3.2 CPU Control Registers
SR: ALU STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HSC DC bit 8 R/W-0, HSC(1) R/W-0, HSC(1) IPL1
(2)
REGISTER 3-1:
U-0 -- bit 15 R/W-0, HSC(1) IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8
(2)
R-0, HSC RA
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC N OV Z C bit 0
IPL0
(2)
HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU Interrupt priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation, which effects the Z bit, has set it at some time in the past 0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit (MSb) of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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REGISTER 3-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/C-0, HSC IPL3(1) R/W-0 PSV U-0 -- U-0 -- bit 0
CORCON: CPU CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as `0' User interrupts are disabled when IPL3 = 1. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware division for 16-bit divisor.
bit 2
bit 1-0 Note 1:
3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: * * * * * * * 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned
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3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT
The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2.
The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
TABLE 3-2:
Instruction ASR SL LSR
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits.
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4.0 MEMORY ORGANIZATION
FIGURE 4-1:
As with Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and busing. This architecture also allows the direct access of program memory from the data space during code execution.
PROGRAM SPACE MEMORY MAP FOR PIC24F04KA201 FAMILY DEVICES
PIC24F04KA200/201
GOTO Instruction Reset Address Interrupt Vector Table Reserved
4.1
Program Address Space
The user access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24F04KA201 family of devices is displayed in Figure 4-1.
User Memory Space
The program address memory space of the PIC24F devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 "Interfacing Program and Data Memory Spaces".
Flash Program Memory (1408 instructions)
Unimplemented Read `0'
Configuration Memory Space
Reserved
Device Config Registers
Reserved
DEVID (2)
Note:
Memory areas are not displayed to scale.
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4.1.1 PROGRAM MEMORY ORGANIZATION
The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. device interrupt sources to be handled by separate ISRs. Section 7.1 "Interrupt Vector (IVT) Table" discusses the interrupt vector tables more in detail.
4.1.3
DEVICE CONFIGURATION WORDS
Table 4-1 provides the addresses of the device Configuration Words for the PIC24F04KA201 family. Their location in the memory map is displayed in Figure 4-1. Refer to Section 23.1 "Configuration Bits" for more information on device Configuration Words.
TABLE 4-1:
DEVICE CONFIGURATION WORDS FOR PIC24F04KA201 FAMILY DEVICES
Configuration Word Addresses F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010
Configuration Word FBS FGS FOSCSEL FOSC FWDT FPOR FICD FDS
4.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000104h to 0001FFh. These vector tables allow each of the many
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
msw Address 000001h 000003h 000005h 000007h most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (lsw Address)
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4.2 Data Address Space
4.2.1 DATA SPACE WIDTH
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is displayed in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility (PSV) area (see Section 4.3.3 "Reading Data From Program Memory Using Program Space Visibility"). PIC24F04KA201 family devices implement a total of 768 words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24F04KA201 FAMILY DEVICES
MSB Address 0001h 07FFh 0801h Implemented Data RAM MSB SFR Space LSB LSB Address 0000h 07FEh 0800h SFR Space Near Data Space
Data RAM 0DFFh 1FFF Unimplemented Read as `0' 7FFFh 8001h 7FFFh 8000h 09FEh 1FFEh
Program Space Visibility Area
FFFFh
FFFEh
Note:
Data memory areas are not shown to scale.
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PIC24F04KA201 FAMILY
4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC(R) devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word, which contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, the data memory and the registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register, which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed, but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the LSB. The MSB is not modified. A sign-extend instruction (SE) is provided to allow the users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.
4.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing (MDA) with a 16-bit address field. For PIC24F04KA201 family devices, the entire implemented data memory lies in Near Data Space (NDS).
4.2.4
SFR SPACE
The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by that module. Much of the SFR space contains unused addresses; these are read as `0'. The SFR space, where the SFRs are actually implemented, is provided in Table 4-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is provided in Table 4-3 through Table 4-21.
TABLE 4-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address xx00 xx20 Core Timers I2CTM -- -- -- -- UART -- -- -- -- System/DS/HLVD -- -- Comp -- ADC/CMTU Capture SPI -- -- -- -- NVM/PMD -- -- xx40 xx60 ICN -- -- -- -- -- xx80 Compare xxA0 Interrupts -- -- -- -- -- -- -- -- -- -- -- -- I/O -- -- -- xxC0 xxE0 -- --
000h 100h 200h 300h 400h 500h 600h 700h
Legend: -- = No implemented SFRs in this block.
DS39937B-page 28
Preliminary
(c) 2009 Microchip Technology Inc.
(c) 2009 Microchip Technology Inc.
TABLE 4-3:
File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CPU CORE REGISTERS MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register IPL2 -- IPL1 -- IPL0 -- RA -- N IPL3 OV PSV Z -- C -- 0000 0000 0000 xxxx 0000 0000 xxxx
Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Value Register Program Counter Low Byte Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- REPEAT Loop Counter Register DC --
Preliminary
DS39937B-page 29
PIC24F04KA201 FAMILY
Disable Interrupts Counter Register
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
DS39937B-page 30
PIC24F04KA201 FAMILY
TABLE 4-4:
File Addr Name CNEN1 0060 CNEN2 0062 CNPU1 0068 CNPU2 006A CNPD1 0070 CNPD2 0072 Legend: Note 1:
ICN REGISTER MAP
Bit 15 -- -- -- -- -- -- Bit 14 CN14IE(1) CN30IE CN30PUE CN30PDE Bit 13 CN13IE(1) CN29IE CN29PUE CN29PDE Bit 12 CN12IE -- -- -- Bit 11 CN11IE -- -- -- Bit 10 -- -- -- -- -- -- Bit 9 -- -- -- -- -- -- Bit 8 CN8IE -- CN8PUE -- CN8PDE -- Bit 7 -- CN23IE(1) -- CN23PUE(1) -- CN23PDE(1) Bit 6 CN6IE(1) CN22IE CN22PUE CN22PDE Bit 5 CN5IE(1) CN21IE CN21PUE CN21PDE Bit 4 CN4IE(1) -- -- -- Bit 3 CN3IE -- -- -- Bit 2 CN2IE -- -- -- Bit 1 CN1IE -- -- -- Bit 0 CN0IE -- -- -- All Resets 0000 0000 0000 0000 0000 0000
CN14PUE(1) CN13PUE(1) CN12PUE CN11PUE CN14PDE(1) CN13PDE(1) CN12PDE CN11PDE
CN6PUE(1) CN5PUE(1) CN4PUE(1) CN3PUE CN2PUE CN1PUE CN0PUE CN6PDE(1) CN5PDE(1) CN4PDE(1) CN3PDE CN2PDE CN1PDE CN0PDE
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are not implemented on 14-pin devices.
TABLE 4-5:
File Name INTCON1 INTCON2 IFS0 IFS1 IFS3 IFS4 IEC0 IEC1 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC7 IPC16 IPC18 IPC19 Addr 0080 0082 0084 0086 008A 008C 0094 0096 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B2 00C4 00C8 00CA
INTERRUPT CONTROLLER REGISTER MAP
Bit 15 NSTDIS ALTIVT NVMIF -- -- -- NVMIE -- -- -- -- -- -- -- -- -- -- -- -- -- CPUIRQ Bit 14 -- DISI -- -- -- -- -- -- -- -- T1IP2 T2IP2 NVMIP2 CNIP2 -- -- -- -- -- -- Bit 13 -- -- AD1IF INT2IF -- CTMUIF AD1IE INT2IE -- CTMUIE T1IP1 T2IP1 NVMIP1 CNIP1 -- -- -- -- -- VHOLD Bit 12 -- -- U1TXIF -- -- -- U1TXIE -- -- -- T1IP0 T2IP0 NVMIP0 CNIP0 -- -- -- -- -- -- Bit 11 -- -- U1RXIF -- -- -- U1RXIE -- -- -- -- -- -- -- -- -- -- -- -- -- ILR3 Bit 10 -- -- SPI1IF -- -- -- SPI1IE -- -- -- OC1IP2 -- SPI1IP2 -- CMIP2 -- -- -- -- -- ILR2 Bit 9 -- -- SPF1IF -- -- -- SPF1IE -- -- -- OC1IP1 -- SPI1IP1 -- CMIP1 -- -- -- -- -- ILR1 Bit 8 -- -- T3IF -- -- HLVDIF T3IE -- -- HLVDIE OC1IP0 -- SPI1IP0 -- CMIP0 -- -- -- -- -- ILR0 Bit 7 -- -- T2IF -- -- -- T2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- -- -- -- -- -- -- -- -- IC1IP2 -- SPF1IP2 AD1IP2 MI2C1P2 -- INT2IP2 U1ERIP2 -- CTMUIP2 Bit 5 -- -- -- -- -- -- -- -- -- -- IC1IP1 -- SPF1IP1 AD1IP1 MI2C1P1 -- INT2IP1 U1ERIP1 -- CTMUIP1 Bit 4 Bit 3 Bit 2 STKERR INT2EP OC1IF CMIF -- -- OC1IE CMIE -- -- INT0IP2 -- T3IP2 U1TXIP2 SI2C1P2 INT1IP2 -- -- HLVDIP2 -- Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF -- U1ERIF IC1IE MI2C1IE -- U1ERIE INT0IP1 -- T3IP1 U1TXIP1 SI2C1P1 INT1IP1 -- -- HLVDIP1 -- Bit 0 -- INT0EP INT0IF SI2C1IF -- -- INT0IE SI2C1IE -- -- INT0IP0 -- T3IP0 U1TXIP0 SI2C1P0 INT1IP0 -- -- HLVDIP0 -- All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4044 4444 0004 4440 4440 0004 0040 0000
MATHERR ADDRERR -- -- INT1IF -- -- -- INT1IE -- -- IC1IP0 -- SPF1IP0 AD1IP0 MI2C1P0 -- INT2IP0 U1ERIP0 -- CTMUIP0 -- T1IF CNIF -- -- T1IE CNIE -- -- -- -- -- -- -- -- -- -- -- --
Preliminary
(c) 2009 Microchip Technology Inc.
U1RXIP2 U1RXIP1 U1RXIP0
INTTREG 00E0 Legend:
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2009 Microchip Technology Inc.
TABLE 4-6:
File Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112
TIMER REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS1 TCKPS0 -- TSYNC TCS -- 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 -- -- -- TCS TCS -- -- 0000 0000
Timer1 Register Timer1 Period Register TON -- TSIDL -- -- -- -- -- -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- --
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets FFFF ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
Preliminary
DS39937B-page 31
File Name IC1BUF IC1CON Legend:
Addr 0140 0142
PIC24F04KA201 FAMILY
Input Capture 1 Register -- -- ICSIDL -- -- -- -- -- ICTMR
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-8:
File Name OC1RS OC1R OC1CON Legend: Addr 0180 0182 0184
OUTPUT COMPARE REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets FFFF FFFF -- -- OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Output Compare 1 Secondary Register Output Compare 1 Register -- -- OCSIDL -- -- -- -- -- --
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-9:
File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2CTM REGISTER MAP
Bit 15 -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- Bit 11 -- -- -- -- -- -- Bit 10 -- -- -- A10M BCL -- -- AMSK9 AMSK8 AMSK7 AMSK6 Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 -- -- ACKDT D/A AMSK5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W AMSK2 RSEN RBF AMSK1 SEN TBF AMSK0 1000 0000 0000 AMSK3 0000
DS39937B-page 32
PIC24F04KA201 FAMILY
I2C1 Receive Register I2C1 Transmit Register I2C1 Baud Rate Generator Register ACKEN P AMSK4 RCEN S
I2CSIDL SCLREL IPMIEN
I2C1 Address Register
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-10:
File Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228
UART REGISTER MAP
Bit 15 UARTEN -- -- Bit 14 -- -- -- Bit 13 USIDL -- -- Bit 12 IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- Baud Rate Generator Prescaler Register Bit 8 UEN0 TRMT Bit 7 WAKE URXISEL1 Bit 6 LPBACK URXISEL0 Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 All Resets 0000 0110 0000 0000 0000
PDSEL1 PDSEL0 STSEL FERR OERR URXDA
UTXISEL1 UTXINV UTXISEL0
Preliminary
(c) 2009 Microchip Technology Inc.
UART1 Transmit Register UART1 Receive Register
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-11:
File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Addr 0240 0242 0244 0248
SPI REGISTER MAP
Bit 15 SPIEN -- FRMEN Bit 14 -- -- SPIFSD Bit 13 SPISIDL -- SPIFPOL Bit 12 -- DISSCK -- Bit 11 -- DISSDO -- Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN -- Bit 6 SPIROV CKP -- Bit 5 SRXMPT MSTEN -- Bit 4 SISEL2 SPRE2 -- Bit 3 SISEL1 SPRE1 -- Bit 2 SISEL0 SPRE0 -- Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16 -- SMP -- CKE --
SPI1 Transmit/Receive Buffer
Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2009 Microchip Technology Inc.
TABLE 4-12:
File Name TRISA PORTA LATA ODCA Legend: Note 1: 2: 3: Addr 02C0 02C2 02C4 02C6
PORTA REGISTER MAP
Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 -- -- -- -- Bit 12 -- -- -- -- Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 -- -- -- -- Bit 8 -- -- -- -- Bit 7 -- -- -- -- Bit 6 TRISA6 RA6 LATA6 ODA6 Bit 5(1) -- RA5 -- -- Bit 4 TRISA4 RA4 LATA4 ODA4 Bit 3 Bit 2 Bit 1 TRISA1 RA1 LATA1 ODA1 Bit 0 TRISA0 RA0 LATA0 ODA0 All Resets 00DF xxxx xxxx 0000
TRISA3(2,3) TRISA2(2) RA3(2,3) LATA3(2,3) ODA3(2,3) RA2(2) LATA2(2) ODA2(2)
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit available only when MCLRE = 0. Bits are available only when the primary oscillator is disabled (POSCMD1:POSCMD0 = 00); otherwise read as `0'. Bits are available only when the primary oscillator is disabled or EC mode is selected (POSCMD1:POSCMD0 = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise read as `0'.
TABLE 4-13:
File Name TRISB Addr 02C8 02CC 02CE 1:
PORTB REGISTER MAP
Bit 15 Bit 14 TRISB14 RB14 LATB14 ODB14 Bit 13 Bit 12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 TRISB9 RB9 LATB9 ODB9 Bit 8 TRISB8 RB8 LATB8 ODB8 Bit 7 TRISB7 RB7 LATB7 ODB7 Bit 6 -- -- -- -- Bit 5 -- -- -- -- Bit 4 TRISB4 RB4 LATB4 ODB4 Bit 3 -- -- -- -- Bit 2 Bit 1 Bit 0 All Resets FFFF xxxx xxxx
TRISB15 RB15 LATB15 ODB15
TRISB13(1) TRISB12(1) RB13(1) LATB13(1) ODB13(1) RB12(1) LATB12(1) ODB12(1)
TRISB2(1) TRISB1(1) TRISB0(1) RB2(1) LATB2(1) ODB2(1) RB1(1) LATB1(1) ODB1(1) RB0(1) LATB0(1) ODB(1)0
PORTB 02CA
Preliminary
DS39937B-page 33
LATB ODCB Legend: Note
PIC24F04KA201 FAMILY
0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are not implemented on 14-pin devices.
TABLE 4-14:
File Name Addr
PAD CONFIGURATION REGISTER MAP
Bit 15 -- Bit 14 -- Bit 13 -- Bit 12 -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 8 -- Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 SMBUSDEL Bit 3 OC1TRIS Bit 2 -- Bit 1 -- Bit 0 -- All Resets 0000
PADCFG1 02FC Legend:
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
DS39937B-page 34
PIC24F04KA201 FAMILY
TABLE 4-15:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL Legend: Note 1: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 0330
ADC REGISTER MAP
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC1 -- -- -- -- -- SSRC0 SMPI3 ADCS5 -- PCFG5 CSSL5 -- SMPI2 ADCS4 CH0SA4 PCFG4 CSSL4 -- SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 0000 0000 0000 0000 0000 0000
ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON VCFG2 ADRC CH0NB -- -- -- VCFG1 -- -- -- -- ADSIDL VCFG0 -- -- -- -- -- OFFCAL SAMC4 -- -- -- SAMC3 CH0SB3 -- CSCNA SAMC2 CH0SB2 CSSL10 FORM1 -- SAMC1 CH0SB1 -- -- FORM0 -- SAMC0 CH0SB0 -- -- SSRC2 BUFS -- CH0NA -- --
Preliminary
(c) 2009 Microchip Technology Inc.
PCFG12(1) PCFG11(1) PCFG10 CSSL12(1) CSSL11(1)
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are not implemented on 14-pin devices.
TABLE 4-16:
File Name Addr
CTMU REGISTER MAP
Bit 15 Bit 14 -- ITRIM4 Bit 13 Bit 12 Bit 11 EDGEN ITRIM1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000
CTMUCON 033C CTMUEN CTMUICON 033E Legend: ITRIM5
CTMUSIDL TGEN ITRIM3 ITRIM2
EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM0 IRNG1 IRNG0 -- -- -- -- -- -- -- --
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
(c) 2009 Microchip Technology Inc.
TABLE 4-17:
File Name CMSTAT CVRCON CM1CON CM2CON Legend: Addr 0630 0632 0634 0636
DUAL COMPARATOR REGISTER MAP
Bit 15 CMSIDL -- CON CON Bit 14 -- -- COE COE Bit 13 -- -- CPOL CPOL Bit 12 -- -- CLPWR CLPWR Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 C2EVT -- CEVT CEVT Bit 8 C1EVT -- COUT COUT Bit 7 -- CVREN EVPOL1 EVPOL1 Bit 6 -- CVROE EVPOL0 EVPOL0 Bit 5 -- CVRR -- -- Bit 4 -- CVRSS CREF CREF Bit 3 -- CVR3 -- -- Bit 2 -- CVR2 -- -- Bit 1 C2OUT CVR1 CCH1 CCH1 Bit 0 C1OUT CVR0 CCH0 CCH0 All Resets 0000 0000 0000 0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
TABLE 4-18:
File Name RCON OSCCON CLKDIV OSCTUN Addr 0740 0742 0744 0748 074E 0756
CLOCK CONTROL REGISTER MAP
Bit 15 TRAPR -- ROI -- ROEN HLVDEN Bit 14 Bit 13 Bit 12 -- COSC0 DOZE0 -- ROSEL -- Bit 11 -- -- DOZEN -- RODIV3 -- Bit 10 DPSLP NOSC2 RCDIV2 -- RODIV2 -- Bit 9 -- NOSC1 RCDIV1 -- RODIV1 -- Bit 8 PMSLP NOSC0 RCDIV0 -- RODIV0 -- Bit 7 EXTR CLKLOCK -- -- -- VDIR Bit 6 SWR -- -- -- -- BGVST Bit 5 SWDTEN LOCK -- TUN5 -- IRVST Bit 4 WDTO -- -- TUN4 -- -- Bit 3 SLEEP CF -- TUN3 -- HLVDL3 Bit 2 IDLE -- -- TUN2 -- HLVDL2 Bit 1 BOR -- TUN1 -- HLVDL1 Bit 0 POR -- TUN0 -- HLVDL0 All Resets (Note 1)
IOPUWR SBOREN COSC2 DOZE2 -- -- -- COSC1 DOZE1 -- ROSSLP HLSIDL
SOSCEN OSWEN (Note 2) 3140 0000 0000
Preliminary
DS39937B-page 35
REFOCON HLVDCON Legend: Note 1: 2:
PIC24F04KA201 FAMILY
0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. RCON register Reset values are dependent on type of Reset. OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
TABLE 4-19:
File Name DSCON DSWSRC DSGPR0 DSGPR1 Legend: Note 1: Addr 0758 075A 075C 075E
DEEP SLEEP REGISTER MAP
Bit 15 DSEN -- Bit 14 -- -- Bit 13 -- -- Bit 12 -- -- Bit 11 -- -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- DSINT0 Bit 7 -- DSFLT Bit 6 -- -- Bit 5 -- -- Bit 4 -- DSWDT Bit 3 -- -- Bit 2 -- DSMCLR Bit 1 DSBOR -- Bit 0 RELEASE DSPOR All Resets(1) 0000 0000 0000 0000
Deep Sleep General Purpose Register 0 Deep Sleep General Purpose Register 1
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The Deep Sleep registers are only reset on a VDD POR event.
DS39937B-page 36
PIC24F04KA201 FAMILY
TABLE 4-20:
File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766
NVM REGISTER MAP
Bit 15 WR -- Bit 14 WREN -- Bit 13 WRERR -- Bit 12 PGMONLY -- Bit 11 -- -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- -- Bit 7 -- NVMKEY7 Bit 6 ERASE NVMKEY6 Bit 5 NVMOP5 Bit 4 NVMOP4 Bit 3 NVMOP3 Bit 2 NVMOP2 Bit 1 NVMOP1 Bit 0 NVMOP0 All Resets 0000(1)
NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-21:
File Name PMD1 PMD2 PMD3 PMD4 Legend: Addr 0770 0772 0774 0776
PMD REGISTER MAP
Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 T3MD -- -- -- Bit 12 Bit 11 T2MD T1MD -- -- -- -- -- -- Bit 10 -- -- CMPMD -- Bit 9 -- -- -- -- Bit 8 -- IC1MD -- -- Bit 7 I2C1MD -- -- -- Bit 6 -- -- -- -- Bit 5 U1MD -- -- -- Bit 4 -- -- -- -- Bit 3 SPI1MD -- -- REFOMD Bit 2 -- -- -- CTMUMD Bit 1 -- -- -- HLVDMD Bit 0 ADC1MD OC1MD -- -- All Resets 0000 0000 0000 0000
-- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
Preliminary
(c) 2009 Microchip Technology Inc.
PIC24F04KA201 FAMILY
4.2.5 SOFTWARE STACK
4.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as depicted in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.
Interfacing Program and Data Memory Spaces
The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Apart from the normal execution, the PIC24F architecture provides two methods by which the program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space, PSV Table instructions allow an application to read or write small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word (lsw) of the program word.
The Stack Pointer Limit Value (SPLIM) register, associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' as all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 09FF in RAM, initialize the SPLIM with the value, 09FD. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. Note: A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit (MSb) of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the MSb of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike the table operations, this limits remapping operations strictly to the user memory area.
FIGURE 4-4:
0000h 15
CALL STACK FRAME
0
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16>
W15 (before CALL) W15 (after CALL)
POP : [--W15] PUSH : [W15++]
See Table 4-22 and Figure 4-5 to know how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.
(c) 2009 Microchip Technology Inc.
Preliminary
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TABLE 4-22: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: 2: User 0 0 Program Space Address <23> 0 TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0>(2) xxxx xxxx <22:16> <15> PC<22:1> 0xx xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. PSVPAG can have only one value (`00' to access program memory) on the PIC24F04KA201 family.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter 23 Bits
0
EA Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits
1/0
24 Bits
Select 1 Program Space Visibility(1) (Remapping) 0 PSVPAG 8 Bits
EA
0
15 Bits
23 Bits
User/Configuration Space Select
Byte Select
Note 1: 2:
The LSb of program space addresses is always fixed as `0' in order to maintain word alignment of data in the program and data spaces. Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.
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4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed.
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by 2 for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom' byte, will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper `phantom' byte is selected (byte select = 1).
2.
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FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space Data EA<15:0> TBLPAG 00 23 15 0 000000h 00000000 00000000 00000000 002BFEh 00000000 23 16 8 0
`Phantom' Byte
TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W
800000h
The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are provided; write operations are also valid in the user memory area.
4.3.3
READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be mapped into an 8K word page (in PIC24F08KA1XX devices) and a 16K word page (in PIC24F16KA1XX devices) of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the MSb of the data space EA is `1', and PSV is enabled by setting the PSV bit in the CPU Control (CORCON<2>) register. The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads from this area add an additional cycle to the instruction being executed, since two program memory fetches are required.
Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 4-7), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes.
For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced
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Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 00 23 15 0 000000h
Data Space 0000h Data EA<14:0>
002BFEh
The data in the page designated by PSVPAG is mapped into the upper half of the data memory space....
8000h
PSV Area
...while the lower 15 bits of the EA specify an exact address within the PSV FFFFh area. This corresponds exactly to the same lower 15 bits of the actual program space address.
800000h
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NOTES:
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5.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash programming, refer to the "PIC24F Family Reference Manual", Section 4. "Program Memory" (DS39715).
Real-Time Streaming Protocol (RTSP) is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes) at a time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes) at a time. The NVMOP<1:0> (NVMCON<1:0>) bits decide the erase block size.
The PIC24F04KA201 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.8V. Flash memory can be programmed in three ways: * In-Circuit Serial ProgrammingTM (ICSPTM) * Run-Time Self Programming (RTSP) * Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FXXXX device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGCx and PGDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear/Program Mode Entry Voltage (MCLR/VPP). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or custom firmware to be programmed.
5.1
Table Instructions and Flash Programming
Regardless of the method used, Flash memory programming is done with the table read and write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register, specified in the table instruction, as depicted in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits Using Program Counter 0 Program Counter 0
Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits
User/Configuration Space Select
24-Bit EA
Byte Select
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5.2 RTSP Operation 5.3
The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks and single row write block (96 bytes) are edge-aligned, from the beginning of program memory. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 32 TBLWT instructions are required to write the full row of memory. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing it is not recommended.
Enhanced In-Circuit Serial Programming
Enhanced ICSP uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification.
5.4
Control Registers
There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls the blocks that need to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 5.5 "Programming Operations" for further details.
5.5
Programming Operations
All of the table write operations are single-word writes (two instruction cycles), because only the buffers are written. A programming cycle is required for programming each row.
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished.
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REGISTER 5-1:
R/SO-0, HC WR bit 15 U-0 -- bit 7 Legend: -n = Value at POR `0' = Bit is cleared bit 15 SO = Settable Only bit `1' = Bit is set x = Bit is unknown HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' R/W-0 ERASE R/W-0 NVMOP5
(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0 WRERR R/W-0 PGMONLY U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 NVMOP4
(1)
R/W-0 WREN
R/W-0 NVMOP3
(1)
R/W-0 NVMOP2
(1)
R/W-0 NVMOP1
(1)
R/W-0 NVMOP0(1) bit 0
WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally PGMONLY: Program Only Enable bit Unimplemented: Read as `0' ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<5:0> on the next WR command 0 = Perform the program operation specified by NVMOP<5:0> on the next WR command NVMOP<5:0>: Programming Operation Command Byte bits(1) Erase Operations (when ERASE bit is `1'): 1010xx = Erase entire boot block (including code-protected boot block)(2) 1001xx = Erase entire memory (including boot block, configuration block, general block)(2) 011010 = Program/erase 4 rows of Flash memory(3) 011001 = Program/erase 2 rows of Flash memory(3) 011000 = Program/erase 1 row of Flash memory(3) 0101xx = Erase entire configuration block (except code protection bits) 0011xx = Erase entire general memory block programming operations All other combinations of NVMOP<5:0> are no operation. Available in ICSPTM mode only. Refer to device programming specification. The address in the Table Pointer decides which rows will be erased.
bit 14
bit 13
bit 12 bit 11-7 bit 6
bit 5-0
Note 1: 2: 3:
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5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOP bits (NVMCON<5:0>) to `011000' to configure for row erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 32 instructions from data RAM into the program memory buffers (see Example 5-1). Write the program block to Flash memory: a) Set the NVMOP bits to `011000' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as displayed in Example 5-5.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY ROW - ASSEMBLY LANGUAGE CODE
; ; Initialize NVMCON ; ; ; ; ;
; Set up NVMCON for row erase operation MOV #0x4058, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted
; ; ; ; ; ;
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EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW - `C' LANGUAGE CODE
// C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); offset = &progAddr & 0xFFFF; __builtin_tblwtl(offset, 0x0000); // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 instructions // C30 function to perform unlock // sequence and set WR
NVMCON = 0x4058; asm("DISI #5"); __builtin_write_NVM();
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EXAMPLE 5-3: LOADING THE WRITE BUFFERS - ASSEMBLY LANGUAGE CODE
; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 32nd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0]
EXAMPLE 5-4:
LOADING THE WRITE BUFFERS - `C' LANGUAGE CODE
// C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4001;
// Initialize NVMCON
//Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = &progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address }
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EXAMPLE 5-5:
DISI MOV MOV MOV MOV BSET NOP NOP BTSC BRA #5 #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
INITIATING A PROGRAMMING SEQUENCE - ASSEMBLY LANGUAGE CODE
; Block all interrupts for next 5 instructions ; ; ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence 2 NOPs required after setting WR Wait for the sequence to be completed
NVMCON, #15 $-2
EXAMPLE 5-6:
INITIATING A PROGRAMMING SEQUENCE - `C' LANGUAGE CODE
// C example using MPLAB C30 asm("DISI #5"); __builtin_write_NVM(); // Block all interrupts for next 5 instructions // Perform unlock sequence and set WR
EXAMPLE 5-7:
; Setup MOV MOV MOV MOV MOV TBLWTL TBLWTH ; Setup MOV MOV DISI MOV MOV MOV MOV BSET
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
a pointer to data Program Memory #tblpage(PROG_ADDR), W0 ; W0, TBLPAG ;Initialize PM Page Boundary SFR #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address #LOW_WORD_N, W2 ; #HIGH_BYTE_N, W3 ; W2, [W0] ; Write PM low word into program latch W3, [W0++] ; Write PM high byte into program latch NVMCON for programming one word to data Program Memory #0x4003, W0 ; W0, NVMCON ; Set NVMOP bits to 0011 #5 ; Disable interrupts while the KEY sequence is written #0x55, W0 ; Write the key sequence W0, NVMKEY #0xAA, W0 W0, NVMKEY NVMCON, #WR ; Start the write cycle
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6.0
Note:
RESETS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the "PIC24F Family Reference Manual", Section 40. "Reset with Programmable Brown-out Reset" (DS39728).
Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states.
The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * * POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDTR: Watchdog Timer Reset BOR: Brown-out Reset Low-Power BOR/Deep Sleep BOR TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset
All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>) which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer (WDT) and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.
Figure 6-1 displays a simplified block diagram of the Reset module.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle POR SYSRST
VDD Rise Detect BOREN<1:0> 0 RCON SLEEP 1 00 01 10 11 VDD Brown-out Reset
BOR
Trap Conflict Illegal Opcode Uninitialized W Register
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REGISTER 6-1:
R/W-0, HS TRAPR bit 15 R/W-0, HS EXTR bit 7
RCON: RESET CONTROL REGISTER(1)
R/W-0 SBOREN U-0 -- U-0 -- R/C-0, HS DPSLP U-0 -- R/W-0 PMSLP bit 8 R/W-1, HS POR bit 0
R/W-0, HS IOPUWR
R/W-0, HS SWR
R/W-0, HS SWDTEN(2)
R/W-0, HS WDTO
R/W-0, HS SLEEP
R/W-0, HS IDLE
R/W-1, HS BOR
Legend: R = Readable bit -n = Value at POR bit 15
C = Clearable bit W = Writable bit `1' = Bit is set
HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13
bit 12-11 bit 10
bit 9 bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred SBOREN: Software Enable/Disable of BOR bit 1 = BOR is turned on in software 0 = BOR is turned off in software Unimplemented: Read as `0' DPSLP: Deep Sleep Mode Flag bit 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred Unimplemented: Read as `0' PMSLP: Program Memory Power During Sleep/Idle bit 1 = Program memory bias voltage remains powered during Sleep/Idle 0 = Program memory bias voltage is powered down during Sleep/Idle EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred
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REGISTER 6-1:
bit 0
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.
Note 1: 2:
TABLE 6-1:
RESET FLAG BIT OPERATION
Setting Event Trap Conflict Event Illegal Opcode or Uninitialized W Register Access Configuration Mismatch Reset MCLR Reset RESET Instruction WDT Time-out PWRSAV #SLEEP Instruction PWRSAV #IDLE Instruction POR, BOR POR PWRSAV #SLEEP instruction with DSCON set Clearing Event POR POR POR POR POR PWRSAV Instruction, POR POR POR -- -- POR
Flag Bit TRAPR (RCON<15>) IOPUWR (RCON<14>) CM (RCON<9>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) DPSLP (RCON<10>) Note:
All Reset flag bits may be set or cleared by the user software.
6.1
Clock Source Selection at Reset
TABLE 6-2:
If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 8.0 "Oscillator Configuration" for further details.
OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant FNOSC Configuration bits (FNOSC<10:8>) COSC Control bits (OSCCON<14:12>)
Reset Type POR BOR MCLR WDTO SWR
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6.2 Device Reset Times
The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.
TABLE 6-3:
Reset Type POR(6)
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Clock Source EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL SYSRST Delay TPOR + TPWRT TPOR + TPWRT TPOR + TPWRT TPOR + TPWRT TPOR + TPWRT TPOR+ TPWRT TPOR + TPWRT TPWRT TPWRT TPWRT TPWRT TPWRT TPWRT TPWRT -- System Clock Delay -- TFRC TLPRC TLOCK TFRC + TLOCK TOST TOST + TLOCK -- TFRC TLPRC TLOCK TFRC + TLOCK TOST TFRC + TLOCK -- 1, 2 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 3, 4 1, 2, 5 1, 2, 4, 5 2 2, 3 2, 3 2, 4 2, 3, 4 2, 5 2, 3, 4 None Notes
BOR
EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL
All Others Note 1: 2: 3: 4: 5:
Any Clock
TPOR = Power-on Reset delay. TPWRT = 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero. TFRC and TLPRC = RC Oscillator start-up times. TLOCK = PLL lock time. TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing oscillator clock to the system. 6: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. For detailed operating frequency and timing specifications, see Section 29.0 "Electrical Characteristics".
Note:
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6.3 Brown-out Reset (BOR)
6.3.2 DETECTING BOR
The PIC24F04KA201 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the and (BOREN<1:0>) Configuration bits (FPOR<6:5,1:0>). There are a total of four BOR configurations, which are provided in Table 6.3.1. The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN<1:0>, except `00'), any drop of VDD below the set threshold point will reset the device. The chip will remain in BOR until VDD rises above threshold. If the Power-up Timer is enabled, it will be invoked after VDD rises above the threshold; it, then, will keep the chip in Reset for an additional time delay, TPWRT, if VDD drops below the threshold while the power-up timer is running. The chip goes back into a BOR and the Power-up Timer will be initialized. Once VDD rises above the threshold, the Power-up Timer will execute the additional time delay. BOR and the Power-up Timer are independently configured. Enabling the BOR Reset does not automatically enable the PWRT. When BOR is enabled, the BOR bit (RCON<1>) is always reset to `1' on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to `0' in the software immediately after any POR event. If the BOR bit is `1' while POR is `0', it can be reliably assumed that a BOR event has occurred. Note: Even when the device exits from Deep Sleep mode, both the POR and BOR are set.
6.3.3
DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, BOR remains under hardware control and operates as previously described. However, whenever the device enters Sleep mode, BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current.
6.3.1
SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<13>). Setting SBOREN enables the BOR to function as previously described. Clearing the SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise, it is read as `0'. Placing BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the BOR configuration. It also allows the user to tailor the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: Even when the BOR is under software control, the BOR Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It can not be changed in software.
6.3.4
DEEP SLEEP BOR (DSBOR)
Deep Sleep BOR is a very low-power BOR circuitry. Due to low current consumption, accuracy may vary. DSBOR occurs anywhere between 1.55V and 1.95V. DSBOR is selected in configuration through the BORV<1:0> (FPOR<6:5>) bits = 00. DSBOR re-arms the POR anywhere between 1.55V and 1.95V; however, below 1.55V, the POR is asserted.
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6.3.5 POR AND LONG OSCILLATOR START-UP TIMES
6.4
Special Function Register Reset States
The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). * The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.
Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word (FOSCSEL); see Table 6-2. The RCFGCAL and NVMCON registers are only affected by a POR.
6.3.6
FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS
6.5
Deep Sleep BOR (DSBOR)
If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR).
Deep Sleep BOR is a very low-power BOR circuitry, used when the device is in Deep Sleep mode. Due to low-current consumption, accuracy may vary. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring FDS = 1. DSLPBOR will re-arm the POR to ensure the device will reset if VDD drops below the POR threshold.
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7.0
Note:
INTERRUPT CONTROLLER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the "PIC24F Family Reference Manual", Section 8. "Interrupts" (DS39707).
vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24F04KA201 family devices implement non-maskable traps and unique interrupts; these are summarized in Table 7-1 and Table 7-2.
The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. It has the following features: * Up to eight processor exceptions and software traps * Seven user-selectable priority levels * Interrupt Vector Table (IVT) with up to 118 vectors * Unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Fixed interrupt entry and return latencies
7.2
Reset Sequence
7.1
Interrupt Vector (IVT) Table
The IVT is displayed in Figure 7-1. The IVT resides in the program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of eight non-maskable trap vectors, plus, up to 118 sources of interrupt. In general, each interrupt source has its own
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset, which forces the Program Counter (PC) to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects the program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.
FIGURE 7-1:
PIC24F INTERRUPT VECTOR TABLE
Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 000000h 000002h 000004h
Decreasing Natural Order Priority
000014h
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh
Note 1:
See Table 7-2 for the interrupt vector list.
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TABLE 7-1:
0 1 2 3 4 5 6 7
TRAP VECTOR DETAILS
IVT Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 000112h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved Trap Source
Vector Number
TABLE 7-2:
IMPLEMENTED INTERRUPT VECTORS
Vector Number 13 18 77 0 20 29 17 16 1 19 72 15 2 9 10 3 7 8 65 11 12 IVT Address 00002Eh 000038h 0000AEh 000014h 00003Ch 00004Eh 000036h 000034h 000016h 00003Ah 0000A4h 000032h 000018h 000026h 000028h 00001Ah 000022h 000024h 000096h 00002Ah 00002Ch AIVT Address 00012Eh 000138h 0001AEh 000114h 00013Ch 00014Eh 000136h 000134h 000116h 00013Ah 0001A4h 000132h 000118h 000126h 000128h 00011Ah 000122h 000124h 000196h 00012Ah 00012Ch Interrupt Bit Locations Flag IFS0<13> IFS1<2> IFS4<13> IFS0<0> IFS1<4> IFS1<13> IFS1<1> IFS1<0> IFS0<1> IFS1<3> IFS4<8> IFS0<15> IFS0<2> IFS0<9> IFS0<10> IFS0<3> IFS0<7> IFS0<8> IFS4<1> IFS0<11> IFS0<12> Enable IEC0<13> IEC1<2> IEC4<13> IEC0<0> IEC1<4> IEC1<13> IEC1<1> IEC1<0> IEC0<1> IEC1<3> IEC4<8> IEC0<15> IEC0<2> IEC0<9> IEC0<10> IEC0<3> IEC0<7> IEC0<8> IEC4<1> IEC0<11> IEC0<12> Priority IPC3<6:4> IPC4<10:8> IPC19<6:4> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC4<6:4> IPC4<2:0> IPC0<6:4> IPC4<14:12> IPC17<2:0> IPC3<14:12> IPC0<10:8> IPC2<6:4> IPC2<10:8> IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0>
Interrupt Source ADC1 Conversion Done Comparator Event CTMU External Interrupt 0 External Interrupt 1 External Interrupt 2 I2C1 Master Event I2C1 Slave Event Input Capture1 Input Change Notification HLVD High/Low-Voltage Detect NVM - NVM Write Complete Output Compare 1 SPI1 Error SPI1 Event Timer1 Timer2 Timer3 UART1 Error UART1 Receiver UART1 Transmitter
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7.3 Interrupt Control and Status Registers
The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into the Vector Number (VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence listed in Table 7-2. For example, the INT0 (External Interrupt 0) is depicted as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the INT0IP<2:0> priority bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU STATUS register (SR) contains the IPL<2:0> bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that the trap events cannot be masked by the user's software. All interrupt registers are described in Register 7-1 through Register 7-18, in the following sections.
The PIC24F04KA201 family of devices implements a total of 23 registers for the interrupt controller: INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 * INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the AIV table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals, or external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. * * * * *
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REGISTER 7-1:
U-0 -- bit 15 R/W-0, HSC IPL2(2,3) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 7-5 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HSC IPL1(2,3) R/W-0, HSC IPL0(2,3) R-0, HSC RA(1) R/W-0, HSC N(1) R/W-0, HSC OV(1) R/W-0, HSC Z(1)
SR: ALU STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC DC(1) bit 8 R/W-0, HSC C(1) bit 0
Unimplemented: Read as `0' IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Bit 8 and bits 4 through 0 are described in Section 3.0 "CPU".
Note 1: 2: 3: Note:
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REGISTER 7-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/C-0, HSC IPL3
(2)
CORCON: CPU CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PSV
(1)
U-0 --
U-0 -- bit 0
Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Unimplemented: Read as `0' See Register 3-1 for the description of this bit, which is not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. Bit 2 is described in Section 3.0 "CPU".
bit 1-0 Note 1: 2: Note:
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REGISTER 7-3:
R/W-0 NSTDIS bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0, HS MATHERR R/W-0, HS ADDRERR R/W-0, HS STKERR R/W-0, HS OSCFAIL U-0 -- bit 0
INTCON1: INTERRUPT CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled Unimplemented: Read as `0' MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0'
bit 14-5 bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 7-4:
R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER2
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0 DISI
R-0, HSC
ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge
bit 14
bit 13-3 bit 2
bit 1
bit 0
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REGISTER 7-5:
R/W-0, HS NVMIF bit 15 R/W-0, HS T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0 -- R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS INT0IF bit 0
U-0 --
U-0 --
U-0 --
R/W-0, HS T1IF
R/W-0, HS OC1IF
R/W-0, HS IC1IF
HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4 bit 3
bit 2
bit 1
bit 0
NVMIF: NVM Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 7-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0 -- R/W-0, HS INT2IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-0, HS INT1IF R/W-0, HS CNIF R/W-0, HS CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0
HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
bit 12-5 bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 7-7:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HS U1ERIF U-0 -- bit 0
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0 -- R/W-0, HS CTMUIF U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HS HLVDIF bit 8
Unimplemented: Read as `0' CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0'
bit 12-9 bit 8
bit 7-2 bit 1
bit 0
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REGISTER 7-8:
R/W-0 NVMIE bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 -- R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0
U-0 --
U-0 --
U-0 --
R/W-0 T1IE
R/W-0 OC1IE
R/W-0 IC1IE
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4 bit 3
bit 2
bit 1
bit 0
NVMIE: NVM Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled
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REGISTER 7-9:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0 -- R/W-0 INT2IE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-0 INT1IE R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 12-5 bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as `0' INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C1IE: Master I2C1 Event Interrupt Enable Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IE: Slave I2C1 Event Interrupt Enable Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred
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REGISTER 7-10:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 U1ERIE U-0 -- bit 0
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 -- R/W-0 CTMUIE U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 HLVDIE bit 8
Unimplemented: Read as `0' CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0'
bit 12-9 bit 8
bit 7-2 bit 1
bit 0
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REGISTER 7-11:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC1IP2 R/W-0 IC1IP1 R/W-0 IC1IP0 U-0 -- R/W-1 INT0IP2 R/W-0 INT0IP1
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
R/W-0 T1IP1 R/W-0 T1IP0 U-0 -- R/W-1 OC1IP2 R/W-0 OC1IP1 R/W-0 OC1IP0 bit 8 R/W-0 INT0IP0 bit 0
R/W-1 T1IP2
Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 7-12:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
R/W-0 T2IP1 R/W-0 T2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8
R/W-1 T2IP2
Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 11-0
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REGISTER 7-13:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPF1IP2 R/W-0 SPF1IP1 R/W-0 SPF1IP0 U-0 -- R/W-1 T3IP2 R/W-0 T3IP1
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
R/W-0 U1RXIP1 R/W-0 U1RXIP0 U-0 -- R/W-1 SPI1IP2 R/W-0 SPI1IP1 R/W-0 SPI1IP0 bit 8 R/W-0 T3IP0 bit 0
R/W-1 U1RXIP2
Unimplemented: Read as `0' U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 7-14:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 AD1IP2 R/W-0 AD1IP1 R/W-0 AD1IP0 U-0 -- R/W-1 U1TXIP2 R/W-0 U1TXIP1
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
R/W-0 NVMIP1 R/W-0 NVMIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 U1TXIP0 bit 0
R/W-1 NVMIP2
Unimplemented: Read as `0' NVMIP<2:0>: NVM Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11-7 bit 6-4
bit 3 bit 2-0
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REGISTER 7-15:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C1P2 R/W-0 MI2C1P1 R/W-0 MI2C1P0 U-0 -- R/W-1 SI2C1P2 R/W-0 SI2C1P1
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
R/W-0 CNIP1 R/W-0 CNIP0 U-0 -- R/W-1 CMIP2 R/W-0 CMIP1 R/W-0 CMIP0 bit 8 R/W-0 SI2C1P0 bit 0
R/W-1 CNIP2
Unimplemented: Read as `0' CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1P<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
bit 11 bit 10-8
bit 7 bit 6-4
bit 3 bit 2-0
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REGISTER 7-16:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT1IP2 R/W-0 INT1IP1
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT1IP0 bit 0
Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
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REGISTER 7-17:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT2IP2 R/W-0 INT2IP1 R/W-0 INT2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 7-18:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U1ERIP2 R/W-0 U1ERIP1 R/W-0 U1ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
Unimplemented: Read as `0' U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 7-19:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 HLVDIP2 R/W-0 HLVDIP1
IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 HLVDIP0 bit 0
Unimplemented: Read as `0' HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled
REGISTER 7-20:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4
IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
R/W-1 CTMUIP2
R/W-0 CTMUIP1
R/W-0 CTMUIP0
U-0 --
U-0 --
U-0 --
U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 7-21:
R-0 CPUIRQ bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 VECNUM<6:0> bit 0 R-0 R-0 R-0
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 -- R/W-0 VHOLD U-0 -- R-0 R-0 ILR<3:0> bit 8 R-0 R-0
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will happen when the CPU priority is higher than the interrupt priority) 0 = No interrupt request is left unacknowledged Unimplemented: Read as `0' VHOLD: Allows Vector Number Capture and Changes what Interrupt is Stored in VECNUM bit 1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current interrupt 0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) Unimplemented: Read as `0' ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 * * * 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as `0' VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 * * * 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8
bit 14 bit 13
bit 12 bit 11-8
bit 7 bit 6-0
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7.4
7.4.1
1. 2.
Interrupt Setup Procedures
INITIALIZATION
7.4.3
TRAP SERVICE ROUTINE (TSR)
To configure an interrupt source: Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4.
A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR.
7.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.
To enable user interrupts, the POP instruction may be used to restore the previous SR value. Only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period. Level 7 interrupt sources are not disabled by the DISI instruction.
3. 4.
Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (i.e., C or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.
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8.0
Note:
OSCILLATOR CONFIGURATION
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Oscillator Configuration, refer to the "PIC24F Family Reference Manual", Section 38. "Oscillator with 500 kHz Low-Power FRC" (DS39726).
* Software-controllable switching between various clock sources. * Software-controllable postscaler for selective clocking of CPU for system power savings. * System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown. Figure 8-1 provides a simplified diagram of the oscillator system.
The oscillator system for the PIC24F04KA201 family of devices has the following features: * A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. * On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources.
FIGURE 8-1:
PIC24F04KA201 FAMILY CLOCK DIAGRAM
Primary Oscillator OSCO XT, HS, EC
REFOCON<15:8> Reference Clock Generator REFO
OSCI
4 x PLL 8 MHz 4 MHz
XTPLL, HSPLL ECPLL,FRCPLL
8 MHz FRC Oscillator 500 kHz LPFRC Oscillator
Postscaler
FRCDIV Peripherals
CLKDIV<10:8>
FRC CLKO
31 kHz (nominal)
Postscaler
LPRC Oscillator
LPRC CPU
Secondary Oscillator SOSCO SOSCEN Enable Oscillator SOSC
CLKDIV<14:12> Clock Control Logic Fail-Safe Clock Monitor
SOSCI
WDT, PWRT, DSWDT Clock Source Option for Other Modules
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8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR
The system clock source can be provided by one of four sources: * Primary Oscillator (POSC) on the OSCI and OSCO pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24F04KA201 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit. * Fast Internal RC (FRC) Oscillator - 8 MHz FRC Oscillator - 500 kHz Lower Power FRC Oscillator * Low-Power Internal RC (LPRC) Oscillator The primary oscillator and 8 MHz FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. The oscillator source (and operating mode) that is used at a device Power-on Reset (POR) event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 23.1 "Configuration Bits" for further details). The Primary Oscillator Configuration bits, POSCMD<1:0> (FOSC<1:0>), and the Initial Oscillator Select Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), select the oscillator source that is used at a POR. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The EC mode frequency range Configuration bits, POSCFREQ<1:0> (FOSC<4:3>), optimize power consumption when running in EC mode. The default configuration is "frequency range is greater than 8 MHz". The Configuration bits allow users to choose between the various clock modes, shown in Table 8-1.
8.2.1
CLOCK SWITCHING MODE CONFIGURATION BITS
The FCKSM Configuration bits (FOSC<7:6>) are used jointly to configure device clock switching and the FSCM. Clock switching is enabled only when FCKSM1 is programmed (`0'). The FSCM is enabled only when FCKSM<1:0> are both programmed (`00').
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Internal Internal POSCMD<1:0> 11 11 11 00 10 00 10 01 00 11 11 FNOSC<2:0> 111 110 101 100 011 011 010 010 010 001 000 1 1 Note 1, 2 1 1 1
8 MHz FRC Oscillator with Postscaler (FRCDIV) 500 MHz FRC Oscillator with Postscaler (LPFRCDIV) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (HS) with PLL Module (HSPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) 8 MHz FRC Oscillator with PLL Module (FRCPLL) 8 MHz FRC Oscillator (FRC) Note 1: 2:
OSCO pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device.
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8.3 Control Registers
The operation of the oscillator is controlled by three Special Function Registers (SFRs): * OSCCON * CLKDIV * OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The Clock Divider register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The FRC Oscillator Tune register (Register 8-3) allows the user to fine tune the FRC oscillator over a range of approximately 12%. Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount.
REGISTER 8-1:
U-0 -- bit 15 R/SO-0, HSC CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12
OSCCON: OSCILLATOR CONTROL REGISTER
R-0, HSC COSC1 R-0, HSC COSC0 U-0 -- R/W-x(1) NOSC2 R/W-x(1) NOSC1 R/W-x(1) NOSC0 bit 8 U-0 -- R-0, HSC(2) LOCK U-0 -- R/CO-0, HS CF U-0 -- R/W-0 SOSCEN R/W-0 OSWEN bit 0 CO = Clear Only bit W = Writable bit `1' = Bit is set SO = Set Only bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown COSC2
R-0, HSC
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits(1) 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) Reset values for these bits are determined by the FNOSC Configuration bits. Also resets to `0' during any valid clock switch or whenever a non-PLL Clock mode is selected.
bit 11 bit 10-8
Note 1: 2:
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REGISTER 8-1:
bit 7
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. Unimplemented: Read as `0' LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled Unimplemented: Read as `0' CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected Unimplemented: Read as `0' SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. Also resets to `0' during any valid clock switch or whenever a non-PLL Clock mode is selected.
bit 6 bit 5
bit 4 bit 3
bit 2 bit 1
bit 0
Note 1: 2:
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REGISTER 8-2:
R/W-0 ROI bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0 DOZE2 R/W-1 DOZE1 R/W-1 DOZE0 R/W-0 DOZEN(1) R/W-0 RCDIV2 R/W-0 RCDIV1 R/W-1 RCDIV0 bit 8
ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU and peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE<2:0>: CPU and Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU and peripheral clock ratio 0 = CPU and peripheral clock ratio set to 1:1 RCDIV<2:0>: FRC Postscaler Select bits When OSCCON (COSC<2:0>) = 111: 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) (default) 000 = 8 MHz (divide by 1) When OSCCON (COSC<2:0>) = 110: 111 = 1.95 kHz (divide by 256) 110 = 7.81 kHz (divide by 64) 101 = 15.62 kHz (divide by 32) 100 = 31.25 kHz (divide by 16) 011 = 62.5 kHz (divide by 8) 010 = 125 kHz (divide by 4) 001 = 250 kHz (divide by 2) (default) 000 = 500 kHz (divide by 1) Unimplemented: Read as `0' This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
bit 14-12
bit 11
bit 10-8
bit 7-0 Note 1:
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REGISTER 8-3:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 TUN5(1) R/W-0 TUN4(1) R/W-0 TUN3(1) R/W-0 TUN2(1) R/W-0 TUN1(1)
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TUN0(1) bit 0
Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 * * * 000001 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 * * * 100001 100000 = Minimum frequency deviation Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic.
Note 1:
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8.4 Clock Switching Operation
With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The primary oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF (OSCCON<3>) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bits value is transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM with LPRC as a clock source is enabled) or SOSC (if SOSCEN remains enabled). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.
2.
3.
8.4.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit in the FOSC Configuration register must be programmed to `0'. (Refer to Section 23.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and FSCM function are disabled. This is the default setting. The NOSCx control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled; it is held at `0' at all times.
4.
5.
6.
8.4.2
OSCILLATOR SWITCHING SEQUENCE
At a minimum, performing a clock switch requires this basic sequence: 1. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON<14:12>), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch.
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The following code sequence for a clock switch is recommended: 1. 2. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock-sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is `0'. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure.
8.5
Reference Clock Output
3.
In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24F04KA201 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 8-4). Setting the ROEN bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON<11:8>) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON<13:12>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the ROSEL bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches.
4.
5. 6. 7.
8.
The core sequence for unlocking the OSCCON register and initiating a clock switch is provided in Example 8-1.
EXAMPLE 8-1:
BASIC CODE SEQUENCE FOR CLOCK SWITCHING
;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0
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REGISTER 8-4:
R/W-0 ROEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
U-0 -- R/W-0 ROSSLP R/W-0 ROSEL R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 8
ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock(1) 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV3:RODIV0: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Unimplemented: Read as `0' The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.
bit 14 bit 13
bit 12
bit 11-8
bit 7-0 Note 1:
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NOTES:
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9.0
Note:
POWER-SAVING FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 39. "Power-Saving Features with Deep Sleep" (DS39727).
The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device.
The PIC24F04KA201 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: * Clock frequency * Instruction-based Sleep, Idle and Deep Sleep modes * Software controlled Doze mode * Selective peripheral control in software Combinations of these methods can be used to selectively tailor an application's power consumption, while still maintaining critical application features, such as timing-sensitive communications.
Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up".
9.2.1
SLEEP MODE
Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. * The I/O pin directions and states are frozen. * The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock will continue to run in Sleep mode if the WDT with LPRC as a clock source is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of these events: * On any interrupt source that is individually enabled * On any form of device Reset * On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered.
9.1
Clock Frequency and Clock Switching
PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 "Oscillator Configuration".
9.2
Instruction-Based Power-Saving Modes
PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals except DSWDT. It also freezes I/O states and removes power to SRAM and Flash memory.
EXAMPLE 9-1:
PWRSAV PWRSAV BSET PWRSAV
PWRSAV INSTRUCTION SYNTAX
; ; ; ; Put the device into SLEEP mode Put the device into IDLE mode Enable Deep Sleep Put the device into Deep SLEEP mode
#SLEEP_MODE #IDLE_MODE DSCON, #DSEN #SLEEP_MODE
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9.2.2 IDLE MODE 9.2.4.1 Entering Deep Sleep Mode
Idle mode has these features: * The CPU will stop executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 "Selective Peripheral Module Control"). * If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled * Any device Reset * A WDT time-out On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. Deep Sleep mode is entered by setting the DSEN bit in the DSCON register, and then executing a SLEEP instruction (PWRSAV #SLEEP_MODE) within one instruction cycle to minimize the chance that Deep Sleep will be spuriously entered. If the PWRSAV command is not given within one instruction cycle, the DSEN bit will be cleared by the hardware and must be set again by the software before entering Deep Sleep mode. The DSEN bit is also automatically cleared when exiting the Deep Sleep mode. Note: To re-enter Deep Sleep after a Deep Sleep wake-up, allow a delay of at least 3 TCY after clearing the RELEASE bit.
The sequence to enter Deep Sleep mode is: 1. If the application requires the Deep Sleep WDT, enable it and configure its clock source (see Section 9.2.4.5 "Deep Sleep WDT" for details). If the application requires Deep Sleep BOR, enable it by programming the DSBOREN Configuration bit (FDS<6>). If needed, save any critical application context data by writing it to the DSGPR0 and DSGPR1 registers (optional). Enable Deep Sleep mode by setting the DSEN bit (DSCON<15>). Enter Deep Sleep mode by issuing 3 NOP commands and then a PWRSAV #0 instruction.
2.
9.2.3
INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
3.
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode.
4. 5.
9.2.4
DEEP SLEEP MODE
In PIC24F04KA201 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available, without requiring the use of external switches to completely remove all power from the device. Entry into Deep Sleep mode is completely under software control. Exit from Deep Sleep mode can be triggered from any of the following events: * * * * POR event MCLR event External Interrupt 0 Deep Sleep Watchdog Timer (DSWDT) time-out
Any time the DSEN bit is set, all bits in the DSWSRC register will be automatically cleared.
9.2.4.2
Exiting Deep Sleep Mode
Deep Sleep mode exits on any one of the following events: * POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. * DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. * Assertion (`0') of the MCLR pin. * Assertion of the INT0 pin (if the interrupt was enabled before Deep Sleep mode was entered). The polarity configuration is used to determine the assertion level (`0' or `1') of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode.
The device has a dedicated Deep Sleep Brown-out Reset (DSBOR) and a Deep Sleep Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Sleep, Idle and Doze).
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Note: Any interrupt pending when entering Deep Sleep mode is cleared,
9.2.4.4
I/O Pins During Deep Sleep
Exiting Deep Sleep mode generally does not retain the state of the device and is equivalent to a Power-on Reset (POR) of the device. Exceptions to this include the DSGPRx registers and DSWSRC. Wake-up events that occur from the time Deep Sleep exits until the time the POR sequence completes are ignored, and are not be captured in the DSWAKE register. The sequence for exiting Deep Sleep mode is: 1. After a wake-up event, the device exits Deep Sleep and performs a POR. The DSEN bit is cleared automatically. Code execution resumes at the Reset vector. To determine if the device exited Deep Sleep, read the Deep Sleep bit, DPSLP (RCON<10>). This bit will be set if there was an exit from Deep Sleep mode. If the bit is set, clear it. Determine the wake-up source by reading the DSWAKE register. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCON<1>). If application context data has been saved, read it back from the DSGPR0 and DSGPR1 registers. Clear the RELEASE bit (DSCON<0>).
During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled. Pins that are configured as inputs (TRIS bit set) prior to entry into Deep Sleep remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRIS bit clear) prior to entry into Deep Sleep remain as output pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep. Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON<1>) are reset. If firmware modifies any of these bits or registers, the I/O will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCON<0>) the I/O pins are "released". This causes the I/O pins to take the states configured by their respective TRIS and LAT bit values. This means that keeping the SOSC running after waking up requires the SOSCEN bit to be set before clearing RELEASE. If the Deep Sleep BOR (DSBOR) is enabled, and a DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. If a MCLR Reset event occurs during Deep Sleep, the DSGPRx, DSCON and DSWAKE registers will remain valid and the RELEASE bit will remain set. The state of the SOSC also will be retained. The I/O pins, however, will be reset to their MCLR Reset state. Since RELEASE is still set, changes to the SOSCEN bit (OSCCON<1>) cannot take effect until the RELEASE bit is cleared. In all other Deep Sleep wake-up cases, application firmware must clear the RELEASE bit in order to reconfigure the I/O pins.
2.
3. 4.
5.
6.
9.2.4.3
Saving Context Data with the DSGPR0/DSGPR1 Registers
As exiting Deep Sleep mode causes a POR, most Special Function Registers reset to their default POR values. In addition, because VDDCORE power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1, or data EEPROM (if available). Unlike other SFRs, the contents of these registers are preserved while the device is in Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON<0>).
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9.2.4.5 Deep Sleep WDT 9.2.4.8 Power-on Resets (PORs)
To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS<4>). The postscaler options are programmed by the DSWDTPS<3:0> Configuration bits (FDS<3:0>). The minimum time-out period that can be achieved is 2.1 ms and the maximum is 25.7 days. For more details on the FDS Configuration register and DSWDT configuration options, refer to Section 23.0 "Special Features". VDD voltage is monitored to produce PORs. Since exiting from Deep Sleep functionally looks like a POR, the technique described in Section 9.2.4.7 "Checking and Clearing the Status of Deep Sleep" should be used to distinguish between Deep Sleep and a true POR event. When a true POR occurs, the entire device including all Deep Sleep logic, (Deep Sleep registers, DSWDT, etc.) is reset.
9.2.4.9
Summary of Deep Sleep Sequence
To review, these are the necessary steps involved in invoking and exiting Deep Sleep mode: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Device exits Reset and begins to execute its application code. If DSWDT functionality is required, program the appropriate Configuration bit. Select the appropriate clock(s) for the DSWDT (optional). Enable and configure the DSWDT (optional). Write context data to the DSGPRx registers (optional). Enable the INT0 interrupt (optional). Set the DSEN bit in the DSCON register. Enter Deep Sleep by issuing a PWRSV #SLEEP_MODE command. Device exits Deep Sleep when a wake-up event occurs. The DSEN bit is automatically cleared. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. Read the DSGPRx registers (optional). Once all state related configurations are complete, clear the RELEASE bit. Application resumes normal operation.
9.2.4.6
Switching Clocks in Deep Sleep Mode
The DSWDT may run from either SOSC or the LPRC clock source. This allows the DSWDT to run without requiring both the LPRC and SOSC to be enabled together, reducing power consumption. Under certain circumstances, it is possible for the DSWDT clock source to be off when entering Deep Sleep mode. In this case, the clock source is turned on automatically (if DSWDT is enabled), without the need for software intervention. However, this can cause a delay in the start of the DSWDT counters. In order to avoid this delay when using SOSC as a clock source, the application can activate SOSC prior to entering Deep Sleep mode.
9.2.4.7
Checking and Clearing the Status of Deep Sleep
Upon entry into Deep Sleep mode, the status bit, DPSLP (RCON<10>), becomes set and must be cleared by the software. On power-up, the software should read this status bit to determine if the Reset was due to an exit from Deep Sleep mode and clear the bit if it is set. Of the four possible combinations of DPSLP and POR bit states, three cases can be considered: * Both the DPSLP and POR bits are cleared. In this case, the Reset was due to some event other than a Deep Sleep mode exit. * The DPSLP bit is clear, but the POR bit is set. This is a normal POR. * Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode was exited.
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REGISTER 9-1:
R/W-0 DSEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DSBOR
(2)
DSCON: DEEP SLEEP CONTROL REGISTER(1)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/C-0, HS RELEASE bit 0
DSEN: Deep Sleep Enable bit 1 = Enters Deep Sleep on execution of PWRSAV #0 0 = Enters normal Sleep on execution of PWRSAV #0 Unimplemented: Read as `0' DSBOR: Deep Sleep BOR Event bit(2) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep RELEASE: I/O Pin State Release bit 1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry 0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and LAT bits to control their states All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms POR.
bit 14-2 bit 1
bit 0
Note 1: 2:
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REGISTER 9-2:
U-0 -- bit 15 R/W-0, HS DSFLT bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0, HS DSWDT U-0 -- R/W-0, HS DSMCLR U-0 -- --
DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)
U-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HS DSINT0 bit 8 R/W-0, HS DSPOR(2,3) bit 0
Unimplemented: Read as `0' DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep DSFLT: Deep Sleep Fault Detected bit 1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep Unimplemented: Read as `0' DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep Unimplemented: Read as `0' DSMCLR: MCLR Event bit 1 = The MCLR pin was active and was asserted during Deep Sleep 0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep Unimplemented: Read as `0' DSPOR: Power-on Reset Event bit(2,3) 1 = The VDD supply POR circuit was active and a POR event was detected 0 = The VDD supply POR circuit was not active, or was active but did not detect a POR event All register bits are cleared when the DSCON bit is set. All register bits are reset only in the case of a POR event outside Deep Sleep mode, except the DSPOR bit, which does not reset on a POR event that is caused due to a Deep Sleep exit. Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
bit 7
bit 6-5 bit 4
bit 3 bit 2
bit 1 bit 0
Note 1: 2: 3:
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9.2.5 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS
9.4
Selective Peripheral Module Control
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode is completed. The device will then wake-up from Sleep or Idle mode.
9.3
Doze Mode
Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.
Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * The Peripheral Enable bit, generically named, "XXXEN", located in the module's main control SFR. * The Peripheral Module Disable (PMD) bit, generically named, "XXXMD", located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. Power consumption is reduced, but not by as much as the PMD bits are used. Most peripheral modules have an enable bit; exceptions include capture and compare modules. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, "XXXIDL". By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature disables the module while in Idle mode, allowing further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.
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10.0
Note:
I/O PORTS
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O Ports, refer to the "PIC24F Family Reference Manual", Section 12. "I/O Ports with Peripheral Pin Select (PPS)" (DS39711). Note that the PIC24F04KA201 family devices do not support Peripheral Pin Select features.
When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Data Latch register (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. Note: The I/O pins retain their state during Deep Sleep. They will retain this state at wake-up until the software restore bit (RELEASE) is cleared.
All of the device pins (except VDD and VSS) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity.
10.1
Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 displays how ports are shared with other peripherals and the associated I/O pin to which they are connected.
FIGURE 10-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data I/O 1 0 1 0 Output Enable Output Multiplexers
PIO Module Read TRIS
Output Data
Data Bus WR TRIS
D CK
Q
I/O Pin
TRIS Latch D WR LAT + WR PORT CK Data Latch Read LAT Input Data Read PORT Q
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10.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. disabled. Depending on the device pin count, there are up to 17 external signals (11 on 14-pin devices) that may be selected (enabled) for generating an interrupt request on a change of state. There are six control registers associated with the CN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up/pull-down connected to it. The pull-ups act as a current source that is connected to the pin and the pull-downs act as a current sink to eliminate the need for external resistors when push button or keypad devices are connected. On any pin, only the pull-up resistor or the pull-down resistor should be enabled, but not both of them. If the push button or the keypad is connected to VDD, enable the pull-down, or if they are connected to VSS, enable the pull-up resistors. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. The pull-downs are enabled separately using the CNPD1 and CNPD2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-downs for the corresponding pins. When the internal pull-up is selected, the pin uses VDD as the pull-up source voltage. When the internal pull-down is selected, the pins are pulled down to VSS by an internal resistor. Make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. Note: Pull-ups and pull-downs on change notification pins should always be disabled whenever the port pin is configured as a digital output.
10.2
Configuring Analog Port Pins
The use of the AD1PCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.
10.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP.
10.3
Input Change Notification
The input change notification function of the I/O ports allows the PIC24F04KA201 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are
EXAMPLE 10-1:
MOV MOV NOP; BTSS 0xFF00, W0; W0, TRISBB; PORTB, #13;
PORT WRITE/READ EXAMPLE
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs //Delay 1 cycle //Next Instruction
Equivalent `C' Code
TRISB = 0xFF00; NOP(); if(PORTBbits.RB13 == 1) { } //Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs //Delay 1 cycle // execute following code if PORTB pin 13 is set.
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11.0
Note:
TIMER1
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the "PIC24F Family Reference Manual", Section 14. "Timers" (DS39704).
Figure 11-1 presents a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. 2. 3. 4. 5. 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set the interrupt priority.
The Timer1 module is a 16-bit timer which can operate as a free-running, interval timer/counter. Timer1 can operate in three modes: * 16-Bit Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter Timer1 also supports these features: * Timer Gate Operation * Selectable Prescaler Settings * Timer Operation during CPU Idle and Sleep modes * Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal
FIGURE 11-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
SOSCO/ T1CK SOSCEN SOSCI Gate Sync TCY
TON 1x
2
01
Prescaler 1, 8, 64, 256
00 TGATE TCS
TGATE
1 Set T1IF 0 Reset
Q Q
D CK 0
TMR1 1 Comparator TSYNC Sync
Equal
PR1
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REGISTER 11-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0
T1CON: TIMER1 CONTROL REGISTER
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0'
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3 bit 2
bit 1
bit 0
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12.0
Note:
TIMER2/3
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the "PIC24F Family Reference Manual", Section 14. "Timers" (DS39704).
To configure Timer2/3 for 32-bit operation: 1. 2. 3. 4. 5. Set the T32 bit (T2CON<3> = 1). Select the prescaler ratio for Timer2 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value. PR3 will contain the msw of the value while PR2 contains the lsw. If interrupts are required, set the interrupt enable bit, T3IE; use the priority bits, T3IP<2:0>, to set the interrupt priority. While Timer2 controls the timer, the interrupt appears as a Timer3 interrupt. 6. Set the TON bit (= 1). The timer value, at any point, is stored in the register pair, TMR<3:2>. TMR3 always contains the msw of the count, while TMR2 contains the lsw. To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. Clear the T32 bit in T2CON<3>. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit (TxCON<15> = 1).
The Timer2/3 module is a 32-bit timer, which can also be configured as two independent 16-bit timers with selectable operating modes. As a 32-bit timer, Timer2/3 operates in three modes: * Two independent 16-bit timers (Timer2 and Timer3) with all 16-bit operating modes (except Asynchronous Counter mode) * Single 32-bit timer * Single 32-bit synchronous counter They also support these features: * Timer gate operation * Selectable prescaler settings * Timer operation during Idle and Sleep modes * Interrupt on a 32-bit Period register match * ADC Event Trigger Individually, both of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC event trigger (this is implemented only with Timer3). The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON and T3CON registers. T2CON and T3CON are provided in generic form in Register 12-1 and Register 12-2, respectively. For 32-bit timer/counter operation, Timer2 is the least significant word (lsw) and Timer3 is the most significant word (msw) of the 32-bit timer. Note: For 32-bit operation, T3CON control bits are ignored. Only T2CON control bits are used for setup and control. Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags.
6.
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FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0> 2 Prescaler 1, 8, 64, 256
T2CK Gate Sync TCY TGATE
TON 1x
01
00 TGATE TCS
1 Set T3IF 0 PR3 ADC Event Trigger
Q Q
D CK
PR2
Equal MSB Reset 16
Comparator LSB TMR3 TMR2 Sync
Read TMR2
(1)
Write TMR2(1) 16 TMR3HLD 16 Data Bus<15:0> 16
Note 1:
The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
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FIGURE 12-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0> 2 Prescaler 1, 8, 64, 256
T2CK Gate Sync TGATE TCY 1 Set T2IF 0 Reset TMR2 Q Q D CK
TON 1x
01 00 TCS TGATE
Sync
Equal
Comparator
PR2
FIGURE 12-3:
TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON 1x Prescaler 1, 8, 64, 256 TCKPS<1:0> 2
T3CK
Sync
01 TGATE TCY 1 Set T3IF 0 Reset TMR3 Q Q D CK 00 TCS TGATE
ADC Event Trigger Equal
Comparator
PR3
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REGISTER 12-1:
R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32(1) U-0 -- R/W-0 TCS U-0 -- bit 0
T2CON: TIMER2 CONTROL REGISTER
U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timer2 On bit When T2CON<3> = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T2CON<3> = 0: 1 = Starts 16-bit Timer2 0 = Stops 16-bit Timer2 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer2 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timer2 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 T32: 32-Bit Timer Mode Select bit(1) 1 = Timer2 and Timer3 form a single 32-bit timer 0 = Timer2 and Timer3 act as two 16-bit timers Unimplemented: Read as `0' TCS: Timer2 Clock Source Select bit 1 = External clock from pin, T2CK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3
bit 2 bit 1
bit 0 Note 1:
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REGISTER 12-2:
R/W-0 TON(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE(1) R/W-0 TCKPS1(1) R/W-0 TCKPS0(1) U-0 -- U-0 -- R/W-0 TCS(1) U-0 -- bit 0
T3CON: TIMER3 CONTROL REGISTER
U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8
TON: Timer3 On bit(1) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer3 Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TCS: Timer3 Clock Source Select bit(1) 1 = External clock from the T3CK pin (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON.
bit 14 bit 13
bit 12-7 bit 6
bit 5-4
bit 3-2 bit 1
bit 0 Note 1:
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13.0
Note:
INPUT CAPTURE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Input Capture, refer to the "PIC24F Family Reference Manual", Section 15. "Input Capture" (DS39701).
The PIC24F04KA201 family devices have one input capture channel. The input capture module has multiple operating modes, which are selected via the IC1CON register. The operating modes include: * Capture timer value on every falling edge of input applied at the IC1 pin * Capture timer value on every rising edge of input applied at the IC1 pin * Capture timer value on every 4th rising edge of input applied at the IC1 pin * Capture timer value on every 16th rising edge of input applied at the IC1 pin * Capture timer value on every rising and every falling edge of input applied at the IC1 pin * Device wake-up from capture pin during CPU Sleep and Idle modes The input capture module has a four-level FIFO buffer. The number of capture events required to generate a CPU interrupt can be selected by the user.
The input capture module is used to capture a timer value from one of two selectable time bases upon an event on an input pin. The input capture features are quite useful in applications requiring frequency (Time Period) and pulse measurement. Figure 13-1 depicts a simplified block diagram of the input capture module.
FIGURE 13-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-Bit Timers TMRy TMRx
16
16
1 Prescaler Counter (1, 4, 16) IC1 Pin 3 Edge Detection Logic Clock Synchronizer ICM<2:0> (IC1CON<2:0>) Mode Select ICOV, ICBNE (IC1CON<4:3>) FIFO R/W Logic
0
ICTMR (IC1CON<7>)
IC1BUF ICI<1:0> IC1CON Interrupt Logic
System Bus
Set Flag IC1IF (in IFSn Register)
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13.1 Input Capture Registers
IC1CON: INPUT CAPTURE 1 CONTROL REGISTER
U-0 -- R/W-0 ICSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ICI1 R/W-0 ICI0 R-0, HC ICOV R-0, HC ICBNE R/W-0 ICM2 R/W-0 ICM1 R/W-0 ICM0 bit 0 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 13-1:
U-0 -- bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
Unimplemented: Read as `0' ICSIDL: Input Capture 1 Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode Unimplemented: Read as `0' ICTMR: Input Capture 1 Timer Select bit 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture 1 Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture 1 Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture 1 Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) - ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module turned off
bit 12-8 bit 7
bit 6-5
bit 4
bit 3
bit 2-0
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14.0
Note:
OUTPUT COMPARE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Output Compare, refer to the "PIC24F Family Reference Manual", Section 16. "Output Compare" (DS39706).
10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to `100'. Disabling and re-enabling of the timer and clearing the TMRy register are not required, but may be advantageous for defining a pulse from a known event time boundary. The output compare module does not have to be disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OC1CON register.
14.1
Setup for Single Output Pulse Generation
When the OCM control bits (OC1CON<2:0>) are set to `100', the selected output compare channel initializes the OC1 pin to the low state and generates a single output pulse. To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. Write the values computed in steps 2 and 3 above into the Output Compare 1 register, OC1R, and the Output Compare 1 Secondary register, OC1RS, respectively. Set Timer Period register, PRy, to value equal to or greater than the value in OC1RS, the Output Compare 1 Secondary register. Set the OCM bits to `100' and the OCTSEL (OC1CON<3>) bit to the desired timer source. The OC1 pin state will now be driven low. Set the TON (TyCON<15>) bit to `1', which enables the compare time base to count. Upon the first match between TMRy and OC1R, the OC1 pin will be driven high. When the incrementing timer, TMRy, matches the Output Compare 1 Secondary register, OC1RS, the second and trailing edge (high-to-low) of the pulse is driven onto the OC1 pin. No additional pulses are driven onto the OC1 pin and it remains low. As a result of the second compare match event, the OC1IF interrupt flag bit is set, which will result in an interrupt if it is enabled, by setting the OC1IE bit. For further information on peripheral interrupts, refer to Section 7.0 "Interrupt Controller".
14.2
Setup for Continuous Output Pulse Generation
When the OCM control bits (OC1CON<2:0>) are set to `101', the selected output compare channel initializes the OC1 pin to the low state and generates output pulses on each and every compare match event. For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate time to the rising edge of the output pulse relative to the TMRy start value (0000h). 3. Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in step 2 and 3 above into the Output Compare 1 register, OC1R, and the Output Compare 1 Secondary register, OC1RS, respectively. 5. Set the Timer Period register, PRy, to a value equal to or greater than the value in OC1RS. 6. Set the OCM bits to `101' and the OCTSEL bit to the desired timer source. The OC1 pin state will now be driven low. 7. Enable the compare time base by setting the TON (TyCON<15>) bit to `1'. 8. Upon the first match between TMRy and OC1R, the OC1 pin will be driven high. 9. When the compare time base, TMRy, matches the OC1RS, the second and trailing edge (high-to-low) of the pulse is driven onto the OC1 pin. 10. As a result of the second compare match event, the OC1IF interrupt flag bit is set. 11. When the compare time base and the value in its respective Timer Period register match, the TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated and a continuous stream of pulses is generated indefinitely. The OC1IF flag is set on each OC1RS/TMRy compare match event.
2. 3.
4.
5.
6.
7. 8. 9.
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14.3 Pulse-Width Modulation (PWM) Mode
EQUATION 14-1: CALCULATING THE PWM PERIOD(1)
PWM Period = [(PRy) + 1] * TCY * (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled. A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles.
The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OC1RS register. Write the OC1R register with the initial duty cycle. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Configure the output compare module for one of two PWM Operation modes by writing to the Output Compare Mode bits, OCM<2:0> (OC1CON<2:0>). Set the TMRy prescale value and enable the time base by setting TON (TxCON<15>) = 1. Note: The OC1R register should be initialized before the output compare module is first enabled. The OC1R register becomes a read-only Duty Cycle register when the module is operated in the PWM modes. The value held in OC1R will become the PWM duty cycle for the first PWM period. The contents of the Output Compare 1 Secondary register, OC1RS, will not be transferred into OC1R until a time base period match occurs.
Note:
5.
14.3.2
PWM DUTY CYCLE
6.
The PWM duty cycle is specified by writing to the OC1RS register. The OC1RS register can be written to at any time, but the duty cycle value is not latched into OC1R until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. In PWM mode, OC1R is a read-only register. Some important boundary parameters of the PWM duty cycle include: * If the Output Compare 1 register, OC1R, is loaded with 0000h, the OC1 pin will remain low (0% duty cycle). * If OC1R is greater than PRy (Timer Period register), the pin will remain high (100% duty cycle). * If OC1R is equal to PRy, the OC1 pin will be low for one time base count value and high for all other count values. See Example 14-1 for PWM mode timing details. Table 14-1 provides an example of PWM frequencies and resolutions for a device operating at 10 MIPS.
14.3.1
PWM PERIOD
The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 14-1.
EQUATION 14-2:
CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
log10 Maximum PWM Resolution (bits) = FCY (FPWM * (Timer Prescale Value)) bits log10(2)
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
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EXAMPLE 14-1:
1.
PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) * TCY * (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) * 62.5 ns * 1 PR2 = 306
2.
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits
Note 1:
Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
TABLE 14-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
7.6 Hz 8 FFFFh 16 61 Hz 1 FFFFh 16 122 Hz 1 7FFFh 15 977 Hz 1 0FFFh 12 3.9 kHz 1 03FFh 10 31.3 kHz 1 007Fh 7 125 kHz 1 001Fh 5
PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 14-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
30.5 Hz 8 FFFFh 16 244 Hz 1 FFFFh 16 488 Hz 1 7FFFh 15 3.9 kHz 1 0FFFh 12 15.6 kHz 1 03FFh 10 125 kHz 1 007Fh 7 500 kHz 1 001Fh 5
PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1:
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
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FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OC1IF(1) OC1RS(1)
OC1R(1)
Output Logic 3
SQ R Output Enable
OC1(1)
Comparator 0 16 1 16 OCTSEL 0 1
OCM<2:0> Mode Select
OCFA(2)
TMR Register Inputs from Time Bases(3)
Period Match Signals from Time Bases(3)
Note 1: 2: 3:
Where `x' is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. OCFA pin controls OC1 channel. Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module.
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14.4 Output Compare Register
OC1CON: OUTPUT COMPARE 1 CONTROL REGISTER
U-0 -- R/W-0 OCSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R-0, HC OCFLT R/W-0 OCTSEL R/W-0 OCM2 R/W-0 OCM1 R/W-0 OCM0 bit 0 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 14-1:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
Unimplemented: Read as `0' OCSIDL: Stop Output Compare 1 in Idle Mode Control bit 1 = Output Compare 1 will halt in CPU Idle mode 0 = Output Compare 1 will continue to operate in CPU Idle mode Unimplemented: Read as `0' OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) OCTSEL: Output Compare 1 Timer Select bit 1 = Timer3 is the clock source for Output Compare 1 0 = Timer2 is the clock source for Output Compare 1 Refer to the device data sheet for specific time bases available to the output compare module. OCM<2:0>: Output Compare 1 Mode Select bits 111 = PWM mode on OC1, Fault pin; OFCA enabled(1) 110 = PWM mode on OC1, Fault pin; OFCA disabled(1) 101 = Initialize OC1 pin low, generate continuous output pulses on OC1 pin 100 = Initialize OC1 pin low, generate single output pulse on OC1 pin 011 = Compare event toggles OC1 pin 010 = Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled OCFA pin controls OC1 channel.
bit 12-5 bit 4
bit 3
bit 2-0
Note 1:
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REGISTER 14-2:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 SMBUSDEL
(2)
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OC1TRIS
(1)
U-0 --
U-0 --
U-0 --
R/W-0 -- bit 0
Unimplemented: Read as `0' OC1TRIS: OC1 Output Tri-State Select bit(1) 1 = OC1 output will not be active on the pin; OCPWM1 can still be used for internal triggers 0 = OC1 output will be active on the pin based on the OCPWM1 module settings Unimplemented: Read as `0' To enable the actual OC1 output, the OCPWM1 module has to be enabled. Bit 4 is described in Section 16.0 "Inter-Integrated Circuit (I2CTM)".
bit 2-0 Note 1: 2:
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15.0
Note:
SERIAL PERIPHERAL INTERFACE (SPI)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Serial Peripheral Interface, refer to the "PIC24F Family Reference Manual", Section 23. "Serial Peripheral Interface (SPI)" (DS39699).
The devices of the PIC24F04KA201 family offer one SPI module on a device. Note: In this section, the SPI module is referred to as SPI1, or separately as SPI1. Special Function Registers (SFRs) will follow a similar notation. For example, SPI1CON1 or SPI1CON2 refers to the control register for the SPI1 module.
To set up the SPI module for the Standard Master mode of operation: 1. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register to set the interrupt priority. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1. Clear the SPIROV bit (SPI1STAT<6>). Enable SPI operation by setting the SPIEN bit (SPI1STAT<15>). Write the data to be transmitted to the SPI1BUF register. Transmission (and reception) will start as soon as data is written to the SPI1BUF register.
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial data EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola's SPI and SIOP interfaces. The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPI1BUF register in either Standard or Enhanced Buffer mode.
2.
3. 4. 5.
The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. The SPI serial interface consists of four pins:
* * * * SDI1: Serial Data Input SDO1: Serial Data Output SCK1: Shift Clock Input or Output SS1: Active-Low Slave Select or Frame Synchronization I/O Pulse
To set up the SPI module for the Standard Slave mode of operation: 1. 2. Clear the SPI1BUF register. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IP bits in the IPC2 register to set the interrupt priority. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit (SPI1CON1<7>) must be set to enable the SS1 pin. Clear the SPIROV bit (SPI1STAT<6>). Enable SPI operation by setting the SPIEN bit (SPI1STAT<15>).
The SPI module can be configured to operate using 2, 3 or 4 pins. In the 3-pin mode, SS1 is not used. In the 2-pin mode, both SDO1 and SS1 are not used. Block diagrams of the module in Standard and Enhanced Buffer modes are displayed in Figure 15-1 and Figure 15-2. 3.
4. 5.
6. 7.
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FIGURE 15-1:
SCK1
SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge
1:1/4/16/64 Primary Prescaler
FCY
SS1/FSYNC1
SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock
SDO1 SDI1 bit 0
SPI1SR
Transfer
Transfer
SPI1BUF
Read SPI1BUF
Write SPI1BUF 16 Internal Data Bus
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To set up the SPI module for the Enhanced Buffer Master (EBM) mode of operation: 1. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1. Clear the SPIROV bit (SPI1STAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPI1CON2<0>). Enable SPI operation by setting the SPIEN bit (SPI1STAT<15>). Write the data to be transmitted to the SPI1BUF register. Transmission (and reception) will start as soon as data is written to the SPI1BUF register. To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 2. Clear the SPI1BUF register. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register to set the interrupt priority. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SS1 pin. Clear the SPIROV bit (SPI1STAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPI1CON2<0>). Enable SPI operation by setting the SPIEN bit (SPI1STAT<15>).
2.
3.
3. 4. 5. 6.
4. 5. 6. 7. 8.
FIGURE 15-2:
SCK1
SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler
FCY
SS1/FSYNC1
SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock
SDO1 SDI1 bit 0
SPI1SR
Transfer
Transfer
8-Level FIFO Receive Buffer
8-Level FIFO Transmit Buffer
SPI1BUF
Read SPI1BUF
Write SPI1BUF 16 Internal Data Bus
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REGISTER 15-1:
R/W-0 SPIEN bit 15 R-0,HSC SRMPT bit 7
SPI1STAT: SPI1 STATUS AND CONTROL REGISTER
U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- R-0, HSC SPIBEC2 R-0, HSC SPIBEC1 R-0, HSC SPIBEC0 bit 8 R-0, HSC SPIRBF bit 0
R/C-0, HS SPIROV
R/W-0, HSC SRXMPT
R/W-0 SISEL2
R/W-0 SISEL1
R/W-0 SISEL0
R-0, HSC SPITBF
Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPI1 Enable bit 1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode Unimplemented: Read as `0' SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode) 1 = SPI1 Shift register is empty and ready to send or receive 0 = SPI1 Shift register is not empty SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPI1BUF register. 0 = No overflow has occurred SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when SPI1 transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPI1SR; as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete 100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot 011 = Interrupt when SPI1 receive buffer is full (SPIRBF bit set) 010 = Interrupt when SPI1 receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT bit is set)
bit 14 bit 13
bit 12-11 bit 10-8
bit 7
bit 6
bit 5
bit 4-2
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REGISTER 15-1:
bit 1
SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED)
bit 0
SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit not yet started, SPI1TXB is full 0 = Transmit started, SPI1TXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPI1BUF location, loading SPI1TXB. Automatically cleared in hardware when SPI1 module transfers data from SPI1TXB to SPI1SR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPI1BUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. SPIRBF: SPI1 Receive Buffer Full Status bit 1 = Receive complete, SPI1RXB is full 0 = Receive is not complete, SPI1RXB is empty In Standard Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to SPI1RXB. Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR.
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REGISTER 15-2:
U-0 -- bit 15 R/W-0 SSEN bit 7
SPI1CON1: SPI1 CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 PPRE0 bit 0
R/W-0 CKP
R/W-0 MSTEN
R/W-0 SPRE2
R/W-0 SPRE1
R/W-0 SPRE0
R/W-0 PPRE1
Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
Unimplemented: Read as `0' DISSCK: Disable SCK1 pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disables SDO1 pin bit 1 = SDO1 pin is not used by module; pin functions as I/O 0 = SDO1 pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPI1 Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPI1 is used in Slave mode. CKE: SPI1 Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable bit (Slave mode) 1 = SS1 pin used for Slave mode 0 = SS1 pin not used by module; pin controlled by port function CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1).
Note 1:
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REGISTER 15-2:
bit 1-0
SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED)
PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1).
Note 1:
REGISTER 15-3:
R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15
SPI1CON2: SPI1 CONTROL REGISTER 2
R/W-0 SPIFPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPIFE R/W-0 SPIBEN bit 0
R/W-0 SPIFSD
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FRMEN: Framed SPI1 Support bit 1 = Framed SPI1 support enabled 0 = Framed SPI1 support disabled SPIFSD: Frame Sync Pulse Direction Control on SS1 Pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode)
bit 14
bit 13
bit 12-2 bit 1
bit 0
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EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FCY FSCK = Primary Prescaler * Secondary Prescaler
Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 15-1:
SAMPLE SCK FREQUENCIES(1,2)
Secondary Prescaler Settings FCY = 16 MHz 1:1 2:1 8000 2000 500 125 4:1 4000 1000 250 63 6:1 2667 667 167 42 8:1 2000 500 125 31
Primary Prescaler Settings
1:1 4:1 16:1 64:1
Invalid 4000 1000 250
FCY = 5 MHz Primary Prescaler Settings 1:1 4:1 16:1 64:1 Note 1: 2: 5000 1250 313 78 2500 625 156 39 1250 313 78 20 833 208 52 13 625 156 39 10
Based on FCY = FOSC/2, Doze mode and PLL are disabled. SCK1 frequencies indicated in kHz.
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16.0
Note:
INTER-INTEGRATED CIRCUIT (I2CTM)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Inter-Integrated Circuit, refer to the "PIC24F Family Reference Manual", Section 24. "Inter-Integrated Circuit (I2CTM)" (DS39702).
2
16.2
Communicating as a Master in a Single Master Environment
The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Assert a Start condition on SDA1 and SCL1. Send the I2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDA1 and SCL1. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDA1 and SCL1.
The Inter-Integrated Circuit (I CTM) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial data EEPROMs, display drivers, A/D Converters, etc. The I2C module supports these features: * * * * * * * * * Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL
Figure 16-1 illustrates a block diagram of the module.
16.1
Pin Remapping Options
The I2C module is tied to a fixed pin. To allow flexibility with peripheral multiplexing, the I2C1 module in 20-pin devices can be reassigned to the alternate pins, designated as SCL1 and SDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins.
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FIGURE 16-1: I2CTM BLOCK DIAGRAM
Internal Data Bus I2C1RCV Shift Clock I2C1RSR LSB SDA1 Address Match
Read
SCL1
Match Detect
Write I2C1MSK Write Read
I2C1ADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic
Write I2C1STAT Read Write I2C1CON
Collision Detect
Acknowledge Generation Clock Stretching
Read
Write
I2C1TRN LSB Shift Clock Reload Control Read
Write I2C1BRG Read
BRG Down Counter
TCY/2
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16.3 Setting Baud Rate When Operating as a Bus Master 16.4 Slave Address Masking
The I2C1MSK register (Register 16-3) designates address bit positions as "don't care" for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the slave module to respond whether the corresponding address bit value is `0' or `1'. For example, when I2C1MSK is set to `00100000', the slave module will detect both addresses: `0000000' and `00100000'. To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the IPMIEN bit (I2C1CON<11>). Note: As a result of changes in the I2C protocol, the addresses in Table 16-2 are reserved and will not be Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses.
To compute the Baud Rate Generator (BRG) reload value, use Equation 16-1.
EQUATION 16-1:
COMPUTING BAUD RATE RELOAD VALUE(1)
FCY FSCL = --------------------------------------------------------------------FCY I2C1BRG + 1 + ----------------------------10, 000, 000 or FCY FCY I2C1BRG = ----------- - ----------------------------- - 1 FSCL 10, 000, 000 Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 16-1:
Required System FSCL 100 kHz 100 kHz 100 kHz 400 kHz 400 kHz 400 kHz 400 kHz 1 MHz 1 MHz 1 MHz Note 1:
I2CTM CLOCK RATES(1)
I2C1BRG Value FCY (Decimal) 16 MHz 8 MHz 4 MHz 16 MHz 8 MHz 4 MHz 2 MHz 16 MHz 8 MHz 4 MHz 157 78 39 37 18 9 4 13 6 3 (Hexadecimal) 9D 4E 27 25 12 9 4 D 6 3 Actual FSCL 100 kHz 100 kHz 99 kHz 404 kHz 404 kHz 385 kHz 385 kHz 1.026 MHz 1.026 MHz 0.909 MHz
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
TABLE 16-2:
Slave Address 0000 000 0000 000 0000 001 0000 010 0000 011 0000 1xx 1111 1xx 1111 0xx Note 1: 2: 3:
I2CTM RESERVED ADDRESSES(1)
R/W Bit 0 1 x x x x x x General Call Address(2) Start Byte Cbus Address Reserved Reserved HS Mode Master Code Reserved 10-Bit Slave Upper Byte(3) Description
The address bits listed here will never cause an address match, independent of the address mask settings. Address will be Acknowledged only if GCEN = 1. Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 16-1:
R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN U-0 --
I2C1CON: I2C1 CONTROL REGISTER
R/W-0 I2CSIDL R/W-1 HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0
I2CEN: I2C1 Enable bit 1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins 0 = Disables the I2C1 module; all I2CTM pins are controlled by port functions Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode SCLREL: SCL1 Release Control bit (when operating as I2C slave) 1 = Releases SCL1 clock 0 = Holds SCL1 clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses Acknowledged 0 = IPMI Support mode is disabled A10M: 10-Bit Slave Addressing bit 1 = I2C1ADD is a 10-bit slave address 0 = I2C1ADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with the SMBus specification 0 = Disables the SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for reception) 0 = General call address disabled STREN: SCL1 Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
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REGISTER 16-1:
bit 5
I2C1CON: I2C1 CONTROL REGISTER (CONTINUED)
ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master; applicable during master receive) 1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware clear at end of master Acknowledge sequence 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C; hardware clear at end of eighth bit of master receive data byte 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware clear at end of master Stop sequence 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware clear at end of master Repeated Start sequence 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDA1 and SCL1 pins; hardware clear at end of master Start sequence 0 = Start condition not in progress
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 16-2:
R-0, HSC ACKSTAT bit 15 R/C-0, HS R/C-0, HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared I2COV R-0, HSC R/C-0, HSC R/C-0, HSC D/A P S R-0, HSC R/W R-0, HSC RBF R-0, HSC TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown R-0, HSC TRSTAT
I2C1STAT: I2C1 STATUS REGISTER
U-0 -- U-0 -- U-0 -- R/C-0, HS BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8
U = Unimplemented bit, read as `0'
ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware set or clear at end of Acknowledge. TRSTAT: Transmit Status bit (When operating as I2CTM master; applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission; hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address; hardware clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address; hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2C1TRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2C1TRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2C1RCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2C1RSR to I2C1RCV (cleared by software). D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was the device address Hardware clear at device address match; hardware set by write to I2C1TRN or by reception of slave byte. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
bit 14
bit 13-11 bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
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REGISTER 16-2:
bit 3
I2C1STAT: I2C1 STATUS REGISTER (CONTINUED)
S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2C1RCV is full 0 = Receive not complete, I2C1RCV is empty Hardware set when I2C1RCV is written with received byte; hardware clear when software reads I2C1RCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware set when software writes to I2C1TRN; hardware clear at completion of data transmission.
bit 2
bit 1
bit 0
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REGISTER 16-3:
U-0 -- bit 15 R/W-0 AMSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 AMSK6 R/W-0 AMSK5 R/W-0 AMSK4 R/W-0 AMSK3 R/W-0 AMSK2 R/W-0 AMSK1
I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AMSK9 R/W-0 AMSK8 bit 8 R/W-0 AMSK0 bit 0
Unimplemented: Read as `0' AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position
REGISTER 16-4:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 U-0 -- U-0 --
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R/W-0 SMBUSDEL R/W-0 OC1TRIS(1,2) U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SMBUSDEL: SMBus SDA Input Delay Select bit 1 = The I2CTM module is configured for a longer SMBus input delay (nominal 300 ns delay) 0 = The 12C module is configured for a legacy input delay (nominal 150 ns delay) Unimplemented: Read as `0' To enable the actual OC1 output, the OCPWM1 module has to be enabled. Bit 3 is described in related chapters.
bit 2-0 Note 1: 2:
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17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the "PIC24F Family Reference Manual", Section 21. "UART" (DS39708). * Fully Integrated Baud Rate Generator (IBRG) with 16-Bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS * 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-Bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is displayed in Figure 17-1. The UART module consists of these important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver
Note:
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. This module also supports a hardware flow control option with the U1CTS and U1RTS pins, and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8-Bit or 9-Bit Data Transmission through the U1TX and U1RX pins * Even, Odd or No Parity Options (for 8-bit data) * One or Two Stop bits * Hardware Flow Control Option with U1CTS and U1RTS pins
FIGURE 17-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA(R)
U1BCLK
Hardware Flow Control
U1RTS U1CTS
UART1 Receiver
U1RX
UART1 Transmitter
U1TX
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17.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The U1BRG register controls the period of a free-running, 16-bit timer. Equation 17-1 provides the formula for computation of the baud rate with BRGH = 0. The maximum baud rate (BRGH = 0) possible is FCY/16 (for U1BRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 provides the formula for computation of the baud rate with BRGH = 1.
EQUATION 17-2:
EQUATION 17-1:
UART BAUD RATE WITH BRGH = 0(1)
FCY 16 * (U1BRG + 1)
UART BAUD RATE WITH BRGH = 1(1)
FCY 4 * (U1BRG + 1) FCY 4 * Baud Rate -1
Baud Rate =
Baud Rate =
U1BRG = U1BRG = Note 1: FCY -1 16 * Baud Rate Note 1:
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Example 17-1 provides the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600
The maximum baud rate (BRGH = 1) possible is FCY/4 (for U1BRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the U1BRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate.
EXAMPLE 17-1:
Desired Baud Rate U1BRG U1BRG U1BRG
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
= FCY/(16 (U1BRG + 1)) = ((FCY/Desired Baud Rate)/16) - 1 = ((4000000/9600)/16) - 1 = 25
Solving for UxBRG value:
Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 = 0.16% Based on FCY = FOSC/2, Doze mode and PLL are disabled.
Note 1:
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17.2
1.
Transmitting in 8-Bit Data Mode
17.5
1. 2. 3.
2. 3. 4.
5.
6.
Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the U1BRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of U1TXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with the next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then, the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISEL1.
Receiving in 8-Bit or 9-Bit Data Mode
4.
5.
Set up the UART (as described in Section 17.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISEL1. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read U1RXREG.
The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values.
17.6
Operation of U1CTS and U1RTS Control Pins
17.3
1. 2. 3. 4. 5.
Transmitting in 9-Bit Data Mode
6.
Set up the UART (as described in Section 17.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write U1TXREG as a 16-bit value only. A word write to U1TXREG triggers the transfer of the 9-bit data to the TSR. The serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISEL1.
UART1 Clear to Send (U1CTS) and Request to Send (U1RTS) are the two hardware-controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control modes. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the U1MODE register configure these pins.
17.7
Infrared Support
The UART module provides two types of infrared UART support: one is the IrDA clock output to support an external IrDA encoder and decoder device (legacy module support), and the other is the full implementation of the IrDA encoder and decoder. As the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (U1MODE<3>) is `0'.
17.7.1
EXTERNAL IrDA SUPPORT - IrDA CLOCK OUTPUT
17.4
Break and Sync Transmit Sequence
The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK - sets up the Break character. Load the U1TXREG with a dummy character to initiate transmission (value is ignored). Write `55h' to U1TXREG - loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits.
To support external IrDA encoder and decoder devices, the U1BCLK pin (same as the U1RTS pin) can be configured to generate the 16x baud clock. When UEN<1:0> = 11, the U1BCLK pin will output the 16x baud clock if the UART module is enabled; it can be used to support the IrDA codec chip.
17.7.2
BUILT-IN IrDA ENCODER AND DECODER
The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (U1MODE<12>). When enabled (IREN = 1), the receive pin (U1RX) acts as the input from the infrared receiver. The transmit pin (U1TX) acts as the output to the infrared transmitter.
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REGISTER 17-1:
R/W-0 UARTEN bit 15 R/C-0, HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 RXINV R/W-0 BRGH R/W-0 PDSEL1 R/W-0 PDSEL0
U1MODE: UART1 MODE REGISTER
U-0 -- R/W-0 USIDL R/W-0 IREN(1) R/W-0 RTSMD U-0 -- R/W-0(2) UEN1 R/W-0(2) UEN0 bit 8 R/W-0 STSEL bit 0
UARTEN: UART1 Enable bit 1 = UART1 is enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0> 0 = UART1 is disabled; all UART1 pins are controlled by port latches; UART1 power consumption is minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA(R) Encoder and Decoder Enable bit(1) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled RTSMD: Mode Selection for U1RTS Pin bit 1 = U1RTS pin in Simplex mode 0 = U1RTS pin in Flow Control mode Unimplemented: Read as `0' UEN<1:0>: UART1 Enable bits(2) 11 = U1TX, U1RX and U1BCLK pins are enabled and used; U1CTS pin controlled by port latches 10 = U1TX, U1RX, U1CTS and U1RTS pins are enabled and used 01 = U1TX, U1RX and U1RTS pins are enabled and used; U1CTS pin controlled by port latches 00 = U1TX and UxRX pins are enabled and used; U1CTS and U1RTS/U1BCLK pins controlled by port latches WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UART1 Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = U1RX Idle state is `0' 0 = U1RX Idle state is `1' This feature is only available for the 16x BRG mode (BRGH = 0). Bit availability depends on pin availability.
bit 14 bit 13
bit 12
bit 11
bit 10 bit 9-8
bit 7
bit 6
bit 5
bit 4
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REGISTER 17-1:
bit 3
U1MODE: UART1 MODE REGISTER (CONTINUED)
BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is only available for the 16x BRG mode (BRGH = 0). Bit availability depends on pin availability.
bit 2-1
bit 0
Note 1: 2:
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REGISTER 17-2:
R/W-0 UTXISEL1 bit 15 R/W-0 URXISEL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 C = Clearable bit HS = Hardware Settable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 URXISEL0 R/W-0 ADDEN R-1, HSC RIDLE R-0, HSC PERR R-0, HSC FERR R/C-0, HS OERR
U1STA: UART1 STATUS AND CONTROL REGISTER
R/W-0 UTXISEL0 U-0 -- R/W-0, HC UTXBRK R/W-0 UTXEN R-0, HSC UTXBF R-1, HSC TRMT bit 8 R-0, HSC URXDA bit 0
R/W-0 UTXINV
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) UTXINV: IrDA(R) Encoder Transmit Polarity Inversion bit If IREN = 0: 1 = U1TX Idle `0' 0 = U1TX Idle `1' If IREN = 1: 1 = U1TX Idle `1' 0 = U1TX Idle `0' Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit 1 = Transmit enabled, U1TX pin controlled by UART1 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by the PORT register. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer. Receive buffer has one or more characters.
bit 14
bit 12 bit 11
bit 10
bit 9
bit 8
bit 7-6
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REGISTER 17-2:
bit 5
U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED)
ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state) URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 17-3:
U-x -- bit 15 W-x UTX7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0
U1TXREG: UART1 TRANSMIT REGISTER
U-x -- U-x -- U-x -- U-x -- U-x -- U-x -- W-x UTX8 bit 8 W-x UTX0 bit 0
W-x UTX6
W-x UTX5
W-x UTX4
W-x UTX3
W-x UTX2
W-x UTX1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' UTX8: Data of the Transmitted Character bit (in 9-bit mode) UTX<7:0>: Data of the Transmitted Character bits
REGISTER 17-4:
U-0 -- bit 15 R-0, HSC URX7 bit 7
U1RXREG: UART1 RECEIVE REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC URX8 bit 8 R-0, HSC URX0 bit 0
R-0, HSC URX6
R-0, HSC URX5
R-0, HSC URX4
R-0, HSC URX3
R-0, HSC URX2
R-0, HSC URX1
Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0
HSC = Hardware Settable/Clearable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' URX8: Data of the Received Character bit (in 9-bit mode) URX<7:0>: Data of the Received Character bits
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18.0
Note:
HIGH/LOW-VOLTAGE DETECT (HLVD)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the High/Low-Voltage Detect, refer to the "PIC24F Family Reference Manual", Section 36. "High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)" (DS39725).
An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The HLVD Control register (see Register 18-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device.
The High/Low-Voltage Detect module (HLVD) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change.
FIGURE 18-1:
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
VDD
Externally Generated Trip Point
HLVDIN
VDD
HLVDL<3:0>
HLVDEN 16-to-1 MUX
VDIR
Set HLVDIF
Internal Voltage Reference 1.2V Typical
HLVDEN
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REGISTER 18-1:
R/W-0 HLVDEN bit 15 R/W-0 VDIR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 BGVST R/W-0 IRVST U-0 -- R/W-0 HLVDL3 R/W-0 HLVDL2 R/W-0 HLVDL1
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 -- R/W-0 HLSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 HLVDL0 bit 0
HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled Unimplemented: Read as `0' HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the internal reference voltage is stable and the high-voltage detect logic generates the interrupt flag at the specified voltage range 0 = Indicates that the internal reference voltage is unstable and the high-voltage detect logic will not generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be enabled Unimplemented: Read as `0' HLVDL<3:0>: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip point 1(1) 1101 = Trip point 2(1) 1100 = Trip point 3(1) . . . 0000 = Trip point 15(1) For actual trip point, refer to Section 26.0 "Electrical Characteristics".
bit 14 bit 13
bit 12-8 bit 7
bit 6
bit 5
bit 4 bit 3-0
Note 1:
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19.0
Note:
10-BIT HIGH-SPEED A/D CONVERTER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 10-Bit High-Speed A/D Converter, refer to the "PIC24F Family Reference Manual", Section 17. "10-Bit A/D Converter" (DS39705).
A block diagram of the A/D Converter is displayed in Figure 19-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFG<15:13>, AD1PCFG<9:6>). b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>). e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). f) Select interrupt rate (AD1CON2<5:2>). g) Turn on A/D module (AD1CON1<15>). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority.
The 10-bit A/D Converter has the following key features: * * * * * * * * * * * Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 9 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes
2.
On all PIC24F04KA201 family devices, the 10-bit A/D Converter has nine analog input pins, designated AN0 through AN5 and AN10 through AN12. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.
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FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus AVDD VR+ VR Select AVSS VREF+ VREFVINH VINL S/H VR- VR+ DAC 16 VR-
Comparator
VINH AN0 AN1 AN2 AN3 AN4 AN5 AN1 VINL MUX A
10-Bit SAR
Conversion Logic
Data Formatting
ADC1BUF0: ADC1BUFF
AD1CON1 AN10 AN11 AN12 MUX B VBG VBG/2 AN1 VINH AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL
VINL
Sample Control Input MUX Control Pin Config Control
Control Logic
Conversion Control
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REGISTER 19-1:
R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 -- U-0 -- R/W-0 ASAM R/W-0, HSC SAMP
AD1CON1: A/D CONTROL REGISTER 1
U-0 -- R/W-0 ADSIDL U-0 -- U-0 -- U-0 -- R/W-0 FORM1 R/W-0 FORM0 bit 8 R/W-0, HSC DONE bit 0
ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' FORM<1:0>: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as `0' ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.
bit 14 bit 13
bit 12-10 bit 9-8
bit 7-5
bit 4-3 bit 2
bit 1
bit 0
Note 1:
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REGISTER 19-2:
R/W-0 VCFG2 bit 15 R-0, HSC BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13
AD1CON2: A/D CONTROL REGISTER 2
R/W-0 VCFG0 R/W-0 OFFCAL(1) U-0 -- R/W-0 CSCNA U-0 -- U-0 -- bit 8 U-0 -- R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM R/W-0 ALTS bit 0
R/W-0 VCFG1
U = Unimplemented bit, read as `0' HSC = Hardware Settable/Clearable bit W = Writable bit r = Reserved bit' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD bit(1) VRAVSS AVSS External VREF- pin External VREF- pin AVSS
bit 12
bit 11 bit 10
bit 9-8 bit 7
bit 6 bit 5-2
OFFCAL: Offset Calibration 1 = Converts to get the offset calibration value 0 = Coverts to get the actual input value Unimplemented: Read as `0' CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer, 00-07, user should access data in 08-0F Unimplemented: Read as `0' SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
bit 1
bit 0
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>) 0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG contents nor channel input selection. Any analog input switches are disconnected from the A/D converter in this mode. The conversion result is stored by the user software and used to compensate subsequent conversions. This can be done by adding the two's complement of the result obtained with the OFFCAL bit set to all normal A/D conversions.
. . .
Note 1:
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REGISTER 19-3:
R/W-0 ADRC bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 r = Reserved bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1
AD1CON3: A/D CONTROL REGISTER 3
U-0 -- U-0 -- R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0
ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Unimplemented: Read as `0' SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD
bit 14-13 bit 12-8
* * *
bit 7-6 bit 5-0
00001 = 1 TAD 00000 = 0 TAD (not recommended) Unimplemented: Read as `0' ADCS<5:0>: A/D Conversion Clock Select bits 111111 = 32 * TCY
* * *
000001 = TCY 000000 = TCY/2
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-
REGISTER 19-4:
R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15
AD1CHS: A/D INPUT SELECT REGISTER
U-0 -- U-0 -- U-0 -- R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0SA0 bit 0
U-0 --
U-0 --
R/W-0 CH0SA4
R/W-0 CH0SA3
R/W-0 CH0SA2
R/W-0 CH0SA1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14-12 bit 11-8
bit 7
bit 6-5 bit 4-0
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0110 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0010 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0110 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0010 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0
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REGISTER 19-5:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1
AD1PCFG: A/D PORT CONFIGURATION REGISTER
U-0 -- U-0 -- R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 U-0 -- U-0 -- bit 8 R/W-0 PCFG0 bit 0
Unimplemented: Read as `0' PCFG<12:10>: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled; A/D samples pin voltage Unimplemented: Read as `0' PCFG<5:0>: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled; A/D samples pin voltage
bit 9-6 bit 5-0
REGISTER 19-6:
U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-10
AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW)
U-0 -- U-0 -- R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 -- R/W-0 -- bit 8 U-0 -- R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 R/W-0 CSSL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CSSL<12:10>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Unimplemented: Read as `0' CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan
bit 9-6 bit 5-0
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EQUATION 19-1: A/D CONVERSION CLOCK PERIOD(1)
ADCS = TAD -1 TCY
TAD = TCY * (ADCS + 1)
Note 1:
Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.
FIGURE 19-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD ANx VT = 0.6V RIC 250W Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS 5 k (Typical)
Rs VA
CPIN 6-11 pF (Typical)
VT = 0.6V
ILEAKAGE 500 nA
Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD
Note:
CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k.
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FIGURE 19-3:
Output Code (Binary (Decimal))
A/D TRANSFER FUNCTION
11 1111 1111 (1023) 11 1111 1110 (1022)
10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509)
00 0000 0001 (1) 00 0000 0000 (0) 512 * (VR+ - VR-) 1024 1023 * (VR+ - VR-) 1024 VR+ - VR1024 VR+ VR(VINH - VINL) 0 Voltage Level
VR- +
VR- +
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VR- +
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20.0
Note:
COMPARATOR MODULE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the "PIC24F Family Reference Manual", Section 19. "Comparator Module" (DS39710).
The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals `1', the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 20-1. Diagrams of the possible individual comparator configurations are displayed in Figure 20-2. Each comparator has its own control register, CMxCON (Register 20-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 20-2).
The comparator module provides two dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs, as well as a voltage reference input from either the internal band gap reference divided by 2 (VBG/2) or the comparator voltage reference generator.
FIGURE 20-1:
CCH<1:0> CREF
COMPARATOR MODULE BLOCK DIAGRAM
EVPOL<1:0> Trigger/Interrupt Logic CEVT COE
CXINB
Input Select Logic
VINVIN+ C1
CPOL
VBG/2
COUT
C1OUT Pin
EVPOL<1:0> Trigger/Interrupt Logic CEVT COE
CXINA CVREF
CPOL VINVIN+ C2
COUT
C2OUT Pin
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FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS
Comparator Off CON = 0, CREF = x, CCH<1:0> = xx
VINVIN+ COE
-
Cx
Off (Read as `0')
CxOUT Pin
Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00
VINVIN+ COE
Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11 VBG/2
CxOUT Pin CXINA VINVIN+ COE
CXINB CXINA
Cx
Cx
CxOUT Pin
Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00
VINVIN+ COE
Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 11
VINVIN+
CXINB CVREF
Cx
CxOUT Pin
VBG/2 CVREF
Cx
COE
CxOUT Pin
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REGISTER 20-1:
R/W-0 CON bit 15 R/W-0 EVPOL1 bit 7
CMxCON: COMPARATOR x CONTROL REGISTERS
R/W-0 CPOL R/W-0 CLPWR U-0 -- U-0 -- R/W-0 CEVT R-0 COUT bit 8 R/W-0 CCH0 bit 0
R/W-0 COE
R/W-0 EVPOL0
U-0 --
R/W-0 CREF
U-0 --
U-0 --
R/W-0 CCH1
Legend: R = Readable bit -n = Value at POR bit 15
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 14
bit 13
bit 12
bit 11-10 bit 9
bit 8
bit 7-6
bit 5 bit 4
bit 3-2 bit 1-0
CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted CLPWR: Comparator Low-Power Mode Select bit 1 = Comparator operates in Low-Power mode 0 = Comparator does not operate in Low-Power mode Unimplemented: Read as `0' CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as `0' CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin Unimplemented: Read as `0' CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 00 = Inverting input of comparator connects to CxINB pin
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REGISTER 20-2:
R/W-0 CMIDL bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC C2OUT
CMSTAT: COMPARATOR MODULE STATUS REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC C2EVT R-0, HSC C1EVT bit 8 R-0, HSC C1OUT bit 0
CMIDL: Comparator Stop in Idle Mode bit 1 = When device enters Idle mode, the module does not generate interrupts; it is still enabled 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as `0' C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). Unimplemented: Read as `0' C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>).
bit 14-10 bit 9 bit 8 bit 7-2 bit 1 bit 0
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21.0
Note:
COMPARATOR VOLTAGE REFERENCE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator Voltage Reference, refer to the "PIC24F Family Reference Manual", Section 20. "Comparator Voltage Reference Module" (DS39709).
21.1
Configuring the Comparator Voltage Reference
The comparator voltage reference module is controlled through the CVRCON register (Register 21-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output.
FIGURE 21-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD CVRSS = 1
CVRSS = 0
8R
CVR<3:0>
CVREN
R R R 16-to-1 MUX R 16 Steps
CVREF
R R R
CVRR VREFCVRSS = 1
8R
CVRSS = 0 AVSS
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REGISTER 21-1:
U-0 -- bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 CVR0 bit 0
Unimplemented: Read as `0' CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ - VREF0 = Comparator reference source CVRSRC = AVDD - AVSS CVR3:CVR0: Comparator VREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1 and CVRSS = 0: CVREF = (CVR<3:0>/24) * (CVRSRC) When CVRR = 0 and CVRSS = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC) When CVRR = 1 and CVRSS = 1: CVREF = ((CVR<3:0>/24) * (CVRSRC)) + VREFWhen CVRR = 0 and CVRSS = 1: CVREF = (1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)) + VREF-
bit 6
bit 5
bit 4
bit 3-0
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22.0
Note:
CHARGE TIME MEASUREMENT UNIT (CTMU)
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the "PIC24F Family Reference Manual", Section 11. "Charge Time Measurement Unit (CTMU)" (DS39724).
22.1
Measuring Capacitance
The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module's precision current source to calculate capacitance according to the relationship: dV C = I -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output's pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 22-1 displays the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the "PIC24F Family Reference Manual".
The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides charge measurement, accurate differential time measurement between pulse sources and asynchronous pulse generation. Its key features include: * * * * * * Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of one nanosecond Accurate current source suitable for capacitive measurement
Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based touch sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register selects the current range of current source and trims the current.
FIGURE 22-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter Current Source
ANx ANY
CAPP
RPR
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22.2 Measuring Time
Time measurements on the pulse width can be similarly performed using the A/D module's internal capacitor (CAD) and a precision resistor for current calibration. Figure 22-2 displays the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 22-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the "PIC24F Family Reference Manual".
22.3
Pulse Generation and Delay
The CTMU module can also generate an output pulse with edges that are not synchronous with the device's system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module.
FIGURE 22-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT
PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source
ANx
FIGURE 22-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
PIC24F Device CTEDG1 EDG1 CTMU CTPLS
Current Source Comparator C2INB C2
CDELAY
CVREF
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REGISTER 22-1:
R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT
CTMUCON: CTMU CONTROL REGISTER
U-0 -- R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0 EDG1STAT bit 0
CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as `0' CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response
bit 14 bit 13
bit 12
bit 10
bit 10
bit 9
bit 8
bit 7
bit 6-5
bit 4
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REGISTER 22-1:
bit 3-2
CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred
bit 1
bit 0
REGISTER 22-2:
R/W-0 ITRIM5 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
R/W-0 ITRIM4
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Source Range Select bits 11 = 100 x Base current 10 = 10 x Base current 01 = Base current level (0.55 A nominal) 00 = Current source disabled Unimplemented: Read as `0'
bit 9-8
bit 7-0
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23.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device Integration and Programming Diagnostics, refer to the individual sections of the "PIC24F Family Reference Manual" provided below: * Section 9. "Watchdog Timer (WDT)" (DS39697) * Section 36. "High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)" (DS39725) * Section 33. "Programming and Diagnostics" (DS39716)
23.1
Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location, F80000h. A complete list is provided in Table 23-1. A detailed explanation of the various bit functions is provided in Register 23-1 through Register 23-7. The address, F80000h, is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh), which can only be accessed using table reads and table writes.
TABLE 23-1:
Configuration Register FGS FOSCSEL FOSC FWDT FPOR FICD FDS
CONFIGURATION REGISTERS LOCATIONS
Address F80004 F80006 F80008 F8000A F8000C F8000E F80010
PIC24F04KA201 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Emulation
REGISTER 23-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
FGS: GENERAL SEGMENT CONFIGURATION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 GSS0 R/C-1 GWRP bit 0
C = Clearable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security enabled GWRP: General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected
bit 0
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REGISTER 23-2:
R/P-1 IESO bit 7 Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 FNOSC2 R/P-1 FNOSC1 R/P-1 FNOSC0 bit 0
IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Unimplemented: Read as `0' FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV) 111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV)
bit 6-3 bit 2-0
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REGISTER 23-3:
R/P-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 P = Programmable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FOSC: OSCILLATOR CONFIGURATION REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 POSCMD1 R/P-1 POSCMD0 bit 0 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC
R/P-1 FCKSM0
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled SOSCSEL: Secondary Oscillator Select Bit 1 = Secondary oscillator configured for high-power operation 0 = Secondary oscillator configured for low-power operation POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency greater than 8 MHz 10 = Primary oscillator/external clock input frequency between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency less than 100 kHz 00 = Reserved; do not use OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00) 0 = CLKO output disabled POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected
bit 5
bit 4-3
bit 2
bit 1-0
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REGISTER 23-4:
R/P-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FWDT: WATCHDOG TIMER CONFIGURATION REGISTER
U-0 -- R/P-1 FWPSA R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 bit 0
R/P-1 WINDIS
FWDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT disabled 0 = Windowed WDT enabled Unimplemented: Read as `0' FWPSA: WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1
bit 6
bit 5 bit 4
bit 3-0
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REGISTER 23-5:
R/P-1 MCLRE(1) bit 7
FPOR: RESET CONFIGURATION REGISTER
R/P-1 BORV0(2) U-0 -- R/P-1 PWRTEN U-0 -- R/P-1 BOREN1 R/P-1 BOREN0 bit 0
R/P-1 BORV1(2)
Legend: R = Readable bit -n = Value at POR bit 7
P = Programmable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5
bit 4 bit 3
bit 2 bit 1-0
MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin enabled; RA5 input pin disabled 0 = RA5 input pin enabled; MCLR disabled BORV<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset set to lowest voltage 10 = Brown-out Reset 01 = Brown-out Reset set to highest voltage 00 = Low-power Brown-out Reset occurs around 2.0V Unimplemented: Read as `0' PWRTEN: Power-up Timer Enable bit 0 = PWRT disabled 1 = PWRT enabled Unimplemented: Read as `0' BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled 10 = Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled 01 = Brown-out Reset controlled with the SBOREN bit setting 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled The MCLRE fuse can only be changed when using the VPP-Based ICSPTM mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. Refer to the electrical specifications for BOR voltages.
Note 1: 2:
REGISTER 23-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1-0 --
FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER
U-0 U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 FICD1 R/P-1 FICD0 bit 0
P = Programmable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' FICD<1:0:> ICD Pin Select bits 10 = PGC2/PGD2 are used for programming the device 01 = PGC3/PGD3 are used for programming the device 00, 11 = Reserved; do not use
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REGISTER 23-7:
R/P-1 DSWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
FDS: DEEP SLEEP CONFIGURATION REGISTER
U-0 -- U-0 -- R/P-1 R/P-1 R/P-1 R/P-1 bit 0 DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0
R/P-1 DSLPBOR
DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled DSLPBOR: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes) 1 = Deep Sleep BOR enabled in Deep Sleep 0 = Deep Sleep BOR disabled in Deep Sleep Unimplemented: Read as `0' DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) nominal 1110 = 1:536,870,912 (6.4 days) nominal 1101 = 1:134,217,728 (38.5 hours) nominal 1100 = 1:33,554,432 (9.6 hours) nominal 1011 = 1:8,388,608 (2.4 hours) nominal 1010 = 1:2,097,152 (36 minutes) nominal 1001 = 1:524,288 (9 minutes) nominal 1000 = 1:131,072 (135 seconds) nominal 0111 = 1:32,768 (34 seconds) nominal 0110 = 1:8,192 (8.5 seconds) nominal 0101 = 1:2,048 (2.1 seconds) nominal 0100 = 1:512 (528 ms) nominal 0011 = 1:128 (132 ms) nominal 0010 = 1:32 (33 ms) nominal 0001 = 1:8 (8.3 ms) nominal 0000 = 1:2 (2.1 ms) nominal
bit 6
bit 5-4 bit 3-0
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REGISTER 23-8:
U-0 -- bit 23 R FAMID7 bit 15 R DEV7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8
DEVID: DEVICE ID REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16
Unimplemented: Read as `0' FAMID<7:0>: Device Family Identifier bits 00001011 = PIC24F04KA201 family DEV<7:0>: Individual Device Identifier bits 00000000 = PIC24F04KA201 00000010 = PIC24F04KA200
REGISTER 23-9:
U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 23-4 bit 3-0
DEVREV: DEVICE REVISION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R REV3 R REV2 R REV1 R REV0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' REV<3:0>: Minor Revision Identifier bits
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23.2 Watchdog Timer (WDT)
For the PIC24F04KA201 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the Configuration bits, WDTPS<3:0> (FWDT<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.
23.2.1
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the Configuration bit, WINDIS (FWDT<6>), to `0'.
23.2.2
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.
FIGURE 23-1:
SWDTEN FWDTEN
WDT BLOCK DIAGRAM
LPRC Control FWPSA Prescaler (5-Bit/7-Bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS<3:0> Postscaler 1:1 to 1:32.768 WDT Overflow Reset
Wake from Sleep
LPRC Input
All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode
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23.3 Deep Sleep Watchdog Timer (DSWDT)
Write protection is controlled by the GWRP bit for the general segment in the Configuration Word. When this bit is programmed to `0', internal write and erase operations to program memory are blocked.
In PIC24F04KA201 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS<4>). The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler. The postscaler can be selected by the Configuration bits, DSWDTPS<3:0> (FDS<3:0>). When the DSWDT is enabled, the clock source is also enabled. DSWDT is one of the sources that can wake-up the device from Deep Sleep mode.
23.5
In-Circuit Serial Programming
PIC24F04KA201 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
23.4
Program Verification and Code Protection
For all devices in the PIC24F04KA201 family, code protection for the general segment is controlled by the Configuration bit, GSS0. This bit inhibits external reads and writes to the program memory space; this has no direct effect in normal execution mode.
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24.0 DEVELOPMENT SUPPORT
24.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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24.2 MPASM Assembler 24.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
24.6 24.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
24.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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24.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 24.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
24.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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24.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
24.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
24.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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25.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source.
The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand, which is a register `Wb' without any address modifier * The second source operand, which is a literal value * The destination of the result (only if not the same as the first source operand), which is typically a register `Wd' with or without an address modifier The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all of the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter (PC) is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles.
The PIC24F instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Word or byte-oriented operations Bit-oriented operations Literal operations Control operations
Table 25-1 lists the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 25-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand, which is typically a register `Wb' without any address modifier * The second source operand, which is typically a register `Ws' with or without an address modifier * The destination of the result, which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value, `f' * The destination, which could either be the file register, `f', or the W0 register, which is denoted as `WREG' Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple
* The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb')
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TABLE 25-1:
Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0000h...1FFFh} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSB must be `0' Field does not require an entry, may be blank Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
SYMBOLS USED IN OPCODE DESCRIPTIONS
Description
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TABLE 25-2:
Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG BTSC BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4
INSTRUCTION SET OVERVIEW
Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None
1 None (2 or 3) 1 None (2 or 3)
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TABLE 25-2:
Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CALL CALL CLR CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CP0 CP0 CPB CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb - Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb - Ws - C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if Wn = Decimal Adjust Wn f = f -1 WREG = f -1 Wd = Ws - 1 f=f-2 WREG = f - 2 Wd = Ws - 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected
1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z
1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C
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TABLE 25-2:
Assembly Mnemonic GOTO GOTO GOTO INC INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP NOP NOPR POP POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None None None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None
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TABLE 25-2:
Assembly Mnemonic PWRSAV RCALL PWRSAV RCALL RCALL REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP TBLRDH TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog<23:16> to Wd<7:0> # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None
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TABLE 25-2:
Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N
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NOTES:
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26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24F04KA201 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F04KA201 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V Voltage on any combined analog and digital pin, with respect to VSS ........................................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V) Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (1) ..........................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (1) ..............................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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26.1 DC Characteristics
PIC24F04KA201 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 26-1:
3.60V 3.00V Voltage (VDD)
3.60V 3.00V
1.80V
8 MHz Frequency Note:
32 MHz
For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz *(VDD - 1.8) + 8 MHz.
TABLE 26-1:
THERMAL OPERATING CONDITIONS
Rating Symbol TJ TA Min -40 -40 Typ -- -- Max +125 +85 Unit C C
Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: PI/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation
PD
PINT + PI/O
W
PDMAX
(TJ - TA)/JA
W
TABLE 26-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol JA JA JA JA JA JA JA JA Typ 62.4 60 108 71 75 80.2 43 32 Max -- -- -- -- -- -- -- -- Unit C/W C/W C/W C/W C/W C/W C/W C/W Notes 1 1 1 1 1 1 1 1
Package Thermal Resistance, 14-Pin PDIP Package Thermal Resistance, 20-Pin PDIP Package Thermal Resistance, 14-Pin SSOP Package Thermal Resistance, 20-Pin SSOP Package Thermal Resistance, 14-Pin SOIC Package Thermal Resistance, 20-Pin SOIC Package Thermal Resistance, 14-Pin QFN Package Thermal Resistance, 20-Pin QFN Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 1.8 1.5 VSS Typ(1) -- -- -- Max Units 3.6 -- 0.7 V V V Conditions DC CHARACTERISTICS Param Symbol No. DC10 DC12 DC16 VDD VDR VPOR Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal
DC17
SVDD
0.05
--
--
V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms
Note 1: 2:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.
TABLE 26-4:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Symbol No. DC18 VHLVD Characteristic HLVD Voltage on VDD HLVDL<3:0> = 0000 Transition HLVDL<3:0> = 0001 HLVDL<3:0> = 0010 HLVDL<3:0> = 0011 HLVDL<3:0> = 0100 HLVDL<3:0> = 0101 HLVDL<3:0> = 0110 HLVDL<3:0> = 0111 HLVDL<3:0> = 1000 HLVDL<3:0> = 1001 HLVDL<3:0> = 1010 HLVDL<3:0> = 1011 HLVDL<3:0> = 1100 HLVDL<3:0> = 1101 HLVDL<3:0> = 1110 Min -- 1.81 1.85 1.90 1.95 2.06 2.12 2.24 2.31 2.47 2.64 2.74 2.85 2.96 3.22 Typ 1.85 1.90 1.95 2.00 2.05 2.17 2.23 2.36 2.43 2.60 2.78 2.88 3.00 3.12 3.39 Max 1.94 2.00 2.05 2.10 2.15 2.28 2.34 2.48 2.55 2.73 2.92 3.02 3.15 3.28 3.56 Units V V V V V V V V V V V V V V V Conditions
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TABLE 26-5: BOR TRIP POINTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Sym No. DC19 Characteristic BOR Voltage on VDD Transition BOR = 00 BOR = 01 BOR = 10 BOR = 11 Min 1.55 2.92 2.63 1.75 Typ 2 3 2.7 Max Units 2.00 3.25 2.92 V V V V Conditions Valid for LPBOR and DSBOR
1.78 2.01
TABLE 26-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions
DC CHARACTERISTICS Parameter No. Typical(1)
IDD Current DC20 330 -40C DS20a 330 +25C 195 A 1.8V DC20b 330 +60C DC20c 330 +85C 0.5 MIPS, FOSC = 1 MHz DC20d 590 -40C DC20e 590 +25C 365 A 3.3V DC20f 645 +60C DC20g 720 +85C DC22 600 -40C DC22a 600 +25C 363 A 1.8V DC22b 600 +60C DC22c 600 +85C 1 MIPS, FOSC = 2 MHz DC22d 1100 -40C DC22e 1100 +25C 695 A 3.3V DC22f 1100 +60C DC22g 1100 +85C DC23 18 -40C DC23a 18 +25C 16 MIPS, 11 mA 3.3V FOSC = 32 MHz DC23b 18 +60C DC23c 18 +85C DC27 3.40 -40C DC27a 3.40 +25C 2.25 mA 2.5V DC27b 3.40 +60C DC27c 3.40 +85C FRC (4 MIPS), FOSC = 8 MHz DC27d 4.60 -40C DC27e 4.60 +25C 3.05 mA 3.3V DC27f 4.60 +60C DC27g 4.60 +85C Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: * EC mode with clock input driven with a square wave rail-to-rail * I/O configured as outputs driven low * MCLR - VDD * WDT FSCM disabled * SRAM, program and data memory active * All PMD bits set except for modules being measured
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TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max 28 28 28 28 55 55 55 55 Units -40C +25C +60C +85C -40C +25C +60C +85C Conditions DC CHARACTERISTICS Parameter No. IDD Current DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g Note 1: 2: Typical(1)
8
A
1.8V LPRC (31 kHz)
3.3V
15
A
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Operating Parameters: * EC mode with clock input driven with a square wave rail-to-rail * I/O configured as outputs driven low * MCLR - VDD * WDT FSCM disabled * SRAM, program and data memory active * All PMD bits set except for modules being measured
TABLE 26-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Set(2) Conditions
DC CHARACTERISTICS Param No. Typical(1)
Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are DC40 100 -40C DC40a 100 +25C 48 A 1.8V DC40b 100 +60C DC40c 100 +85C 0.5 MIPS, FOSC = 1 MHz DC40d 215 -40C DC40e 215 +25C 106 A 3.3V DC40f 215 +60C DC40g 215 +85C Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: * Core off * EC mode with clock input driven with a square wave rail-to-rail * I/O configured as outputs driven low * MCLR - VDD * WDT FSCM disabled * SRAM, program and data memory active * All PMD bits set except for modules being measured
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TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units
(2)
DC CHARACTERISTICS Param No. Typical(1)
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set DC42 200 -40C DC42a 200 +25C 94 A 1.8V DC42b 200 +60C DC42c 200 +85C 1 MIPS, FOSC = 2 MHz DC42d 395 -40C DC42e 395 +25C 160 A 3.3V DC42f 395 +60C DC42g 395 +85C DC43 6.0 -40C DC43a 6.0 +25C 16 MIPS, 3.1 mA 3.3V FOSC = 32 MHz DC43b 6.0 +60C DC43c 6.0 +85C DC44 0.74 -40C DC44a 0.74 +25C 0.56 mA 1.8V DC44b 0.74 +60C DC44c 0.74 +85C FRC (4 MIPS), FOSC = 8 MHz DC44d 1.50 -40C DC44e 1.50 +25C 0.95 mA 3.3V DC44f 1.50 +60C DC44g 1.50 +85C DC50 18 -40C DC50a 18 +25C 2 A 1.8V DC50b 18 +60C DC50c 18 +85C LPRC (31 kHz) DC50d 40 -40C DC50e 40 +25C 4 A 3.3V DC50f 40 +60C DC50g 40 +85C Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: * Core off * EC mode with clock input driven with a square wave rail-to-rail * I/O configured as outputs driven low * MCLR - VDD * WDT FSCM disabled * SRAM, program and data memory active * All PMD bits set except for modules being measured
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TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60c DC60d DC60e DC60f DC60g DC70 DC70a DC70b DC70c DC70d DC70e DC70f DC70g DC61 DC61a DC61b DC61c DC61d DC61e DC61f DC61g Note 1: 2: 3: 0.87 0.55 0.035 0.020 0.105 0.025 Typical(1)
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is `0'(2) 0.200 0.200 0.870 1.350 0.540 0.540 1.680 2.450 0.150 0.150 0.430 0.630 0.300 0.300 0.700 0.980 0.65 0.65 0.65 0.65 0.95 0.95 0.95 0.95 A A A A A A -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C 3.3V 1.8V Watchdog Timer Current: WDT(3,4) 3.3V 1.8V Base Deep Sleep Current 3.3V 1.8V Base Power-Down Current (Sleep)(3)
Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: 5:
Current applies to Sleep only. Current applies to Deep Sleep only.
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TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC62 DC62a DC62b DC62c DC62d DC62e DC62f DC62g DC64 DC64a DC64b DC64c DC64d DC64e DC64f DC64g DC63 DC63a DC63b DC63c Note 1: 2: 3: 4.5 6.2 5.5 0.730 0.450 Typical(1)
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is `0'(2) 0.650 0.650 0.650 0.650 0.980 0.980 0.980 0.980 7.10 7.10 7.80 8.30 7.10 7.10 7.80 8.30 6.60 6.60 6.60 6.60 A A A A A -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C 3.3V 3.3V 1.8V HLVD(3,4) 3.3V 1.8V Timer1 w/32 kHz Crystal: T132 (SOSC - LP)(3)
BOR(3,4)
Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: 5:
Current applies to Sleep only. Current applies to Deep Sleep only.
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TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC70 DC70a DC70b DC70c DC70d DC70e DC70f DC70g DC71 DC71a DC71b DC71c DC71d DC71e DC71f DC71g DC72 DC72a DC72b DC72c DC72d DC72e DC72f DC72g Note 1: 2: 3: 0.010 0.005 0.55 0.35 0.095 0.045 Typical(1)
Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is `0'(2) 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.55 0.55 0.55 0.55 0.75 0.75 0.75 0.75 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.200 A A A A A A -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V
LPBOR(3,4)
Deep Sleep Watchdog Timer: DSWDT (SOSC - LP)(5)
Deep Sleep BOR: DSBOR(3,5)
Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
4: 5:
Current applies to Sleep only. Current applies to Deep Sleep only.
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TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- VSS VSS VSS VSS VSS VSS -- 0.8 VDD 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 50 Typ(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 Max -- 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 -- VDD VDD VDD VDD VDD VDD VDD VDD 500 Units -- V V V V V V -- V V V V V V V V A 2.5V VPIN VDD VDD = 3.3V, VPIN = VSS SMBus disabled SMBus enabled Conditions DC CHARACTERISTICS Param No. DI10 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2CTM Buffer I/O Pins with SMBus Buffer Input High Voltage(4) I/O Pins: with Analog Functions Digital Only MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2C Buffer: with Analog Functions Digital Only I/O Pins with SMBus ICNPU CNx Pull-up Current IIL DI50 DI51 DI55 DI56 Note 1: 2: Input Leakage Current(2,3) I/O Ports VREF+, VREF-, AN0, AN1 MCLR OSCI -- -- -- -- 0.050 0.300 -- -- 0.100 0.500 5.0 5.0 A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes
DI25 DI26 DI27 DI28
DI29 DI30
3: 4:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pin buffer types.
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TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 DO26 Note 1: Sym VOL Characteristic Output Low Voltage All I/O Pins OSC2/CLKO Output High Voltage All I/O Pins OSC2/CLKO -- -- -- -- -- 3 1.8 3 1.8 -- -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 -- -- -- -- -- V V V V -- V V V V IOL = 6.5 mA, VDD = 3.6V IOL = 3.5 mA, VDD = 2.0V IOL = 8.0 mA, VDD = 3.6V IOL = 4.5 mA, VDD = 1.8V -- IOH = -3.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -2.5 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions
Data in "Typ" column is at 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-11: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS Param No. D130 D131 D132 D133A D134 D135 Note 1: 2: Sym Characteristic Program Flash Memory EP VPR VPEW TIW Cell Endurance VDD for Read Supply Voltage for Self-Timed Writes Self-Timed Write Cycle Time 10,000(2) VMIN 2.2 -- 40 -- -- -- -- 2 -- 10 -- 3.6 3.6 -- -- -- E/W V V ms Year mA Provided no other specifications are violated VMIN = Minimum operating voltage Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions
TRETD Characteristic Retention IDDP Supply Current During Programming
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Self-write and block erase.
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TABLE 26-12: COMPARATOR DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. D300 D301 D302 Symbol VIOFF VICM CMRR Characteristic Input Offset Voltage* Input Common Mode Voltage* Common Mode Rejection Ratio* Min -- 0 55 Typ 20 -- -- Max 40 VDD -- Units mV V dB Comments
* Parameters are characterized but not tested.
TABLE 26-13: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40C < TA < +85C (unless otherwise stated) Param No. Symbol Characteristic Resolution Absolute Accuracy Unit Resistor Value (R) Min VDD/24 -- -- Typ -- -- 2k Max VDD/32 AVDD - 1.5 -- Units LSb LSb Comments
VRD310 CVRES VRD311 CVRAA VRD312 CVRUR
TABLE 26-14: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS Param Sym No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- -- Typ(1) 550 5.5 55 Max -- -- -- Units nA A A Conditions CTMUICON<1:0> = 01 CTMUICON<1:0> = 10 CTMUICON<1:0> = 11
IOUT1 CTMU Current Source, Base Range IOUT2 CTMU Current Source, 10x Range IOUT3 CTMU Current Source, 100x Range Note 1:
Nominal value at center point of current trim range (CTMUICON<7:2> = 000000)
TABLE 26-15: COMPARATOR TIMINGS
Param No. 300 301 * Note 1: Symbol TRESP TMC2OV Characteristic Response Time*(1) Comparator Mode Change to Output Valid* Min -- -- Typ 150 -- Max 400 10 Units ns s Comments
Parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
TABLE 26-16: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Param No. VR310 Note 1: Symbol TSET Characteristic Settling Time(1) Min -- Typ -- Max 10 Units s Comments
Settling time measured while CVRR = 1 and CVR<3:0> bits transition from `0000' to `1111'.
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26.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24F04KA201 family AC characteristics and timing parameters.
TABLE 26-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 26.1 "DC Characteristics".
FIGURE 26-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 - for OSCO
Load Condition 1 - for all pins except OSCO VDD/2 RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output
TABLE 26-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI EC mode In I2CTM mode
DO56 DO58 Note 1:
CIO CB
All I/O Pins and OSCO SCLx, SDAx
-- --
-- --
50 400
pF pF
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
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FIGURE 26-3:
Q4
EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20 OS25 OS30 OS30 OS31 OS31
CLKO
OS40 OS41
TABLE 26-19: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min DC 4 0.2 4 4 31 -- 62.5 0.45 x TOSC -- -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- 6 6 Max 32 8 4 25 8 33 -- DC -- 20 10 10 Units MHz MHz MHz MHz MHz kHz -- ns ns ns ns ns EC EC EC ECPLL XT HS HSPLL SOSC See parameter OS10 for FOSC value Conditions
FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency
OS20 OS25 OS30 OS31 OS40 OS41
TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2)
TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time
(3)
Note 1: 2:
3:
Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 26-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V)
AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range PLL Output Frequency Range Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 4 16 -- -2 Typ(2) -- -- -- 1 Max 8 32 2 2 Units MHz MHz ms % Measured over 100 ms period Conditions ECPLL, HSPLL modes
TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter)
These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F20 Note 1: Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
Internal FRC Accuracy @ 8 MHz(1) FRC -2 -5 -- -- 2 5 % % +25C -40C TA +85C 3.0V VDD 3.6V
Frequency calibrated at 25C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 26-22: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -15 -15 -- -- 15 15 % % +25C -40C TA +85C 3.0V VDD 3.6V Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions
Change of LPRC frequency as VDD changes.
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FIGURE 26-4: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 26-2 for load conditions. New Value
TABLE 26-23: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
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TABLE 26-24: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Param Symbol No. AD01 AVDD Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min. Typ Max. Units Conditions
Device Supply Module VDD Supply Greater of VDD - 0.3 or 1.8 VSS - 0.3 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD - 1.7 AVDD + 0.3 V
AD02 AD05 AD06 AD07
AVSS VREFH VREFL VREF
Module VSS Supply
-- -- -- --
V V V V
Reference Inputs Reference Voltage High AVSS + 1.7 Reference Voltage Low Absolute Reference Voltage AVSS AVSS - 0.3
Analog Input AD10 AD11 AD12 AD17 VINH-VINL Full-Scale Input Span VIN VINL RIN Absolute Input Voltage Absolute VINL Input Voltage Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) VREFL AVSS - 0.3 AVSS - 0.3 -- -- -- -- VREFH AVDD + 0.3 AVDD/2 2.5K V V V 10-bit (Note 2)
ADC Accuracy AD20 b AD21 b AD22 b AD23 b AD24 b AD25 b Note 1: 2: NR INL DNL GERR EOFF -- -- -- -- -- -- 10 1 1 1 1 -- -- 2 1.5 3 2 -- bits LSb LSb LSb LSb -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed
The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.
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TABLE 26-25: ADC CONVERSION TIMING REQUIREMENTS(1)
AC CHARACTERISTICS Param No. AD50 AD51 Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic Min. Typ Max. Units Conditions
Symbol
Clock Parameters TAD TRC ADC Clock Period ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Acquisition Time Switching Time from Convert to Sample Discharge Time Sample Start Delay from setting Sample bit (SAMP) 75 -- -- 250 -- -- ns ns TCY = 75 ns, AD1CON3 in default state
Conversion Rate AD55 AD56 AD57 AD58 AD59 AD60 AD61 Note 1: 2: 3: TCONV FCNV TSAMP TACQ TSWC TDIS TPSS -- -- -- 750 -- 0.5 2 12 -- 1 -- -- -- -- -- 500 -- -- (Note 3) -- 3 TAD TAD TAD ksps TAD ns (Note 2) AVDD 2.7V
Clock Parameters
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). On the following cycle of the device clock.
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TABLE 26-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS Param Symbol No. SY10 SY11 SY12 SY13 SY20 SY25 SY35 SY45 TmcL TPWRT TPOR TIOZ TWDT TBOR TFSCM TRST TVREG SY55 SY65 SY75 SY85 Note 1: TLOCK TOST TFRC TLPRC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Characteristic MCLR Pulse Width (low) Power-up Timer Period Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period Brown-out Reset Pulse Width Fail-Safe Clock Monitor Delay Configuration Update Time On-Chip Voltage Regulator Output Delay PLL Start-up Time Oscillator Start-up Time Fast RC Oscillator Start-up Time Low-Power Oscillator Start-up Time Min. 2 50 1 -- 0.85 3.4 1 -- -- -- -- -- -- -- Typ(1) -- 64 5 -- 1.0 4.0 -- 2 20 10 1 1024 1 -- Max. -- 90 10 100 1.15 4.6 -- 2.3 -- -- -- -- 1.5 100 Units s ms s ns ms ms s s s s ms TOSC s s 1.32 prescaler 1:128 prescaler Conditions
Data in "Typ" column is at 3.3V, 25C unless otherwise stated.
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NOTES:
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27.0
27.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example PIC24F04KA200 -I/P e3 0910017
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
24F4KA e3 0910 017
20-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC24F04KA201-I/P e3 0910017
Legend: XX...X Y YY WW NNN
e3
*
Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example 24F04KA201 -I/SS e3 0910017
20-Lead SOIC (.300")
XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example
PIC24F04KA201 -I/SO e3 0910017
20-Lead QFN
Example
XXXXXX XXXXXX XXXXXX YYWWNNN
24F04 KA201 /MQ e3 0910017
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27.2 Package Details
The following sections give the technical details of the packages.
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20-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
Microchip Technology Drawing C04-120A
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APPENDIX A: REVISION HISTORY
Revision A (February 2009)
Original data sheet for the PIC24F04KA201 family of devices.
Revision B (May 2009)
The title was changed. Section 2.0 "Guidelines for Getting Started with 16-Bit Microcontrollers" was added. Extensive changes to Section 26.0 "Electrical Characteristics". Minor text edits throughout document.
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INDEX
A
A/D 10-Bit High-Speed A/D Converter ............................ 143 Conversion Timing Requirements ............................ 202 Module Specifications .............................................. 201 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements ............................ 203 A/D Converter Analog Input Model .................................................. 150 Transfer Function ..................................................... 151 AC Characteristics Capacitive Loading Requirements on Output Pins ...................................................... 197 Comparator .............................................................. 196 Comparator Voltage Reference Settling Time ............................................ 196, 200 CTMU Current Source ............................................. 196 Internal RC Accuracy ............................................... 199 Load Conditions and Requirements ......................... 197 Temperature and Voltage Specifications ................. 197 Assembler MPASM Assembler .................................................. 174
C
C Compilers MPLAB C18 ............................................................. 174 MPLAB C30 ............................................................. 174 Charge Time Measurement Unit. See CTMU. Code Examples Erasing a Program Memory Row, `C' Language Code ............................................ 47 Erasing a Program Memory Row, Assembly Language Code ................................ 46 I/O Port Write/Read ................................................. 100 Initiating a Programming Sequence, `C' Language Code ............................................ 49 Initiating a Programming Sequence, Assembly Language Code ................................ 49 Loading the Write Buffers, `C' Language Code ......... 48 Loading the Write Buffers, Assembly Language Code ................................................. 48 Programming a Single Word of Flash Program Memory ..................................... 49 PWRSAV Instruction Syntax ..................................... 91 Sequence for Clock Switching ................................... 88 Code Protection ............................................................... 171 Comparator ...................................................................... 153 Comparator Voltage Reference ....................................... 157 Configuring .............................................................. 157 Configuration Bits ............................................................ 163 Core Features ...................................................................... 7 CPU ALU ............................................................................ 23 Control Registers ....................................................... 22 Core Registers ........................................................... 20 Programmer's Model ................................................. 19 CTMU Measuring Capacitance ........................................... 159 Measuring Time ....................................................... 160 Pulse Delay and Generation .................................... 160 Customer Change Notification Service ............................ 218 Customer Notification Service ......................................... 218 Customer Support ............................................................ 218
B
Baud Rate Generator Setting as a Bus Master ........................................... 127 Block Diagrams 10-Bit High-Speed A/D Converter ............................ 144 16-Bit Timer1 ........................................................... 101 Accessing Program Memory with Table Instructions .............................................. 40 CALL Stack Frame ..................................................... 37 Comparator Module ................................................. 153 Comparator Voltage Reference ............................... 157 CPU Programmer's Model ......................................... 21 CTMU Connections and Internal Configuration for Capacitance Measurement ......................... 159 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ....... 160 CTMU Typical Connections and Internal Configuration for Time Measurement .............. 160 Data Access From Program Space Address Generation ........................................... 38 High/Low-Voltage Detect (HLVD) ............................ 141 I2C Module ............................................................... 126 Individual Comparator Configurations ...................... 154 Input Capture ........................................................... 109 Output Compare ...................................................... 114 PIC24F CPU Core ..................................................... 20 PIC24F04KA201 Family (General) ............................ 10 PSV Operation ........................................................... 41 Reset System ............................................................. 51 Shared I/O Port Structure .......................................... 99 Simplified UART ....................................................... 133 SPI1 Module (Enhanced Buffer Mode) .................... 119 SPI1 Module (Standard Buffer Mode) ...................... 118 System Clock ............................................................. 81 Timer2 (16-Bit Synchronous Mode) ......................... 105 Timer2/3 (32-Bit Mode) ............................................ 104 Timer3 (16-Bit Synchronous Mode) ......................... 105 Watchdog Timer (WDT) ........................................... 170 Brown-out Reset (BOR) ..................................................... 55
D
Data Memory Address Space .......................................................... 27 Memory Map .............................................................. 27 Near Data Space ....................................................... 28 Organization .............................................................. 28 SFR Space ................................................................ 28 Software Stack .......................................................... 37 Space Width .............................................................. 27 DC Characteristics Brown-out Reset Trip Points .................................... 188 Comparator .............................................................. 196 Comparator Voltage Reference ............................... 196 High/Low-Voltage Detect ......................................... 187 I/O Pin Input Specifications ..................................... 194 I/O Pin Output Specifications ................................... 195 Idle Current IIDLE ..................................................... 189 Operating Current IDD .............................................. 188 Power-Down Current IPD ......................................... 191 Program Memory ..................................................... 195 Temperature and Voltage Specifications ................. 187
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Deep Sleep BOR (DSBOR) ............................................... 56 Development Support ...................................................... 173 Device Features (Summary) ................................................ 9 Doze Mode ......................................................................... 97
M
Microchip Internet Web Site ............................................. 218 MPLAB ASM30 Assembler, Linker, Librarian .................. 174 MPLAB ICD 2 In-Circuit Debugger .................................. 175 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 175 MPLAB Integrated Development Environment Software ............................................. 173 MPLAB PM3 Device Programmer ................................... 175 MPLAB REAL ICE In-Circuit Emulator System ............... 175 MPLINK Object Linker/MPLIB Object Librarian ............... 174
E
Electrical Characteristics Absolute Maximum Ratings ..................................... 185 Thermal Operating Conditions ................................. 186 V/F Graphs ............................................................... 186 Equations A/D Conversion Clock Period .................................. 150 Baud Rate Reload Value ......................................... 127 Calculating the PWM Period .................................... 112 Calculation for Maximum PWM Resolution .............. 112 Device and SPI Clock Speed Relationship .............. 124 UART Baud Rate with BRGH = 0 ............................ 134 UART Baud Rate with BRGH = 1 ............................ 134 Errata ................................................................................... 5
N
Near Data Space ............................................................... 28
O
Oscillator Configuration Clock Switching ......................................................... 87 Sequence .......................................................... 87 Configuration Values for Clock Selection .................. 82 CPU Clocking Scheme .............................................. 82 Initial Configuration on POR ...................................... 82 Output Compare Continuous Output Pulse Generation ...................... 111 PWM Mode Period and Duty Cycle Calculations ................ 113 Single Output Pulse Generation .............................. 111
F
Flash Program Memory Control Registers ....................................................... 44 Enhanced ICSP Operation ......................................... 44 Operations ................................................................. 44 Programming Algorithm ............................................. 46 RTSP Operation ......................................................... 44 Table Instructions ....................................................... 43
H
High/Low-Voltage Detect (HLVD) .................................... 141
P
Packaging Details ...................................................................... 207 Marking .................................................................... 205 PICSTART Plus Development Programmer .................... 176 Pinout Descriptions ...................................................... 11-13 Power-Saving Features ..................................................... 91 Clock Frequency and Clock Switching ...................... 91 Product Identification System .......................................... 220 Program and Data Memory Access Using Table Instructions ................................ 39 Program Space Visibility ............................................ 40 Program and Data Memory Spaces Interfacing .................................................................. 37 Program Memory Address Space .......................................................... 25 Memory Map .............................................................. 25 Program Verification ........................................................ 171 Pulse-Width Modulation. See PWM.
I
I/O Ports Analog Port Pins Configuration ................................ 100 Input Change Notification ......................................... 100 Open-Drain Configuration ........................................ 100 Parallel (PIO) ............................................................. 99 I2C Clock Rates .............................................................. 127 Communicating as Master in Single Master Environment ......................................... 125 Pin Remapping Options ........................................... 125 Reserved Addresses ................................................ 127 Slave Address Masking ........................................... 127 In-Circuit Serial Programming .......................................... 171 Input Capture ................................................................... 109 Instruction Set Opcode Symbols ...................................................... 178 Overview .................................................................. 179 Summary .................................................................. 177 Instruction-Based Power-Saving Modes ............................ 91 Deep Sleep ................................................................ 92 Idle ............................................................................. 92 Sleep .......................................................................... 91 Inter-Integrated Circuit. See I2C. Internet Address ............................................................... 218 Interrupts Alternate Interrupt Vector Table (AIVT) ..................... 57 Implemented Vectors ................................................. 58 Interrupt Vector Table (IVT) ....................................... 57 Reset Sequence ........................................................ 57 Setup and Service Procedures .................................. 80 Trap Vectors .............................................................. 58 Vector Table ............................................................... 57
R
Reader Response ............................................................ 219 Reference Clock Output .................................................... 88 Register Maps A/D Converter (ADC) ................................................. 34 Clock Control ............................................................. 35 CPU Core .................................................................. 29 CTMU ........................................................................ 34 Deep Sleep ................................................................ 35 Dual Comparator ....................................................... 35 I2C ............................................................................. 32 ICN ............................................................................ 30 Input Capture ............................................................. 31 Interrupt Controller ..................................................... 30 NVM ........................................................................... 36 Output Compare ........................................................ 31 Pad Configuration ...................................................... 33
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PMD ........................................................................... 36 PORTA ....................................................................... 33 PORTB ....................................................................... 33 SPI ............................................................................. 32 Timer .......................................................................... 31 UART ......................................................................... 32 Registers AD1CHS (A/D Input Select) ..................................... 148 AD1CON1 (A/D Control 1) ....................................... 145 AD1CON2 (A/D Control 2) ....................................... 146 AD1CON3 (A/D Control 3) ....................................... 147 AD1CSSL (A/D Input Scan Select, Low) ................. 149 AD1PCFG (A/D Port Configuration) ......................... 149 CLKDIV (Clock Divider) ............................................. 85 CMSTAT (Comparator Status) ................................. 156 CMxCON (Comparator x Control) ............................ 155 CORCON (Core Control) ........................................... 61 CORCON (CPU Control) ........................................... 23 CTMUCON (CTMU Control) .................................... 161 CTMUICON (CTMU Current Control) ...................... 162 CVRCON (Comparator Voltage Reference Control) .......................................... 158 DEVID (Device ID) ................................................... 169 DEVREV (Device Revision) ..................................... 169 DSCON (Deep Sleep Control) ................................... 95 DSWSRC (Deep Sleep Wake-up Source) ................. 96 FDS (Deep Sleep Configuration) ............................. 168 FGS (General Segment Configuration) .................... 163 FICD (In-Circuit Debugger Configuration) ................ 167 FOSC (Oscillator Configuration) .............................. 165 FOSCSEL (Oscillator Selection Configuration) ........ 164 FPOR (Reset Configuration) .................................... 167 FWDT (Watchdog Timer Configuration) .................. 166 HLVDCON (High/Low-Voltage Detect Control) ........ 142 I2C1CON (I2C1 Control) .......................................... 128 I2C1MSK (I2C1 Slave Mode Address Mask) ........... 132 I2C1STAT (I2C1 Status) .......................................... 130 IC1CON (Input Capture 1 Control) ........................... 110 IEC0 (Interrupt Enable Control 0) .............................. 67 IEC1 (Interrupt Enable Control 1) .............................. 68 IEC4 (Interrupt Enable Control 4) .............................. 69 IFS0 (Interrupt Flag Status 0) .................................... 64 IFS1 (Interrupt Flag Status 1) .................................... 65 IFS4 (Interrupt Flag Status 4) .................................... 66 INTCON1 (Interrupt Control 1) ................................... 62 INTTREG (Interrupt Control and Status) .................... 79 IPC0 (Interrupt Priority Control 0) .............................. 70 IPC1 (Interrupt Priority Control 1) .............................. 71 IPC16 (Interrupt Priority Control 16) .......................... 77 IPC18 (Interrupt Priority Control 18) .......................... 78 IPC19 (Interrupt Priority Control 19) .......................... 78 IPC2 (Interrupt Priority Control 2) .............................. 72 IPC3 (Interrupt Priority Control 3) .............................. 73 IPC4 (Interrupt Priority Control 4) .............................. 74 IPC5 (Interrupt Priority Control 5) .............................. 75 IPC7 (Interrupt Priority Control 7) .............................. 76 NVMCON (Flash Memory Control) ............................ 45 OC1CON (Output Compare 1 Control) .................... 115 OSCCON (Oscillator Control) .................................... 83 OSCTUN (FRC Oscillator Tune) ................................ 86 PADCFG1 (Pad Configuration Control) ........... 116, 132 RCON (Reset Control) ............................................... 52 REFOCON (Reference Oscillator Control) ................ 89 SPI1CON1 (SPI1 Control 1) .................................... 122 SPI1CON2 (SPI1 Control 2) .................................... 123 SPI1STAT (SPI1 Status and Control) ...................... 120 SR (ALU STATUS) .............................................. 22, 60 T1CON (Timer1 Control) ......................................... 102 T2CON (Timer2 Control) ......................................... 106 T3CON (Timer3 Control) ......................................... 107 U1MODE (UART1 Mode) ........................................ 136 U1RXREG (UART1 Receive) .................................. 140 U1STA (UART1 Status and Control) ....................... 138 U1TXREG (UART1 Transmit) ................................. 140 Resets Clock Source Selection ............................................. 53 Delay Times ............................................................... 54 Device Times ............................................................. 54 RCON Flags Operation ............................................. 53 SFR States ................................................................ 56 Revision History ............................................................... 213
S
Selective Peripheral Power Control ................................... 97 Serial Peripheral Interface. See SPI. SFR Space ........................................................................ 28 Software Simulator (MPLAB SIM) ................................... 174 Software Stack .................................................................. 37
T
Timer1 ............................................................................. 101 Timer2/3 .......................................................................... 103 Timing Diagrams CLKO and I/O .......................................................... 200 External Clock ......................................................... 198 Timing Requirements CLKO and I/O .......................................................... 200 External Clock ......................................................... 198 PLL Clock Specifications ......................................... 199
U
UART ............................................................................... 133 Baud Rate Generator (BRG) ................................... 134 Break and Sync Transmit Sequence ....................... 135 IrDA Support ............................................................ 135 Operation of U1CTS and U1RTS Control Pins ........ 135 Receiving in 8-Bit or 9-Bit Data Mode ..................... 135 Transmitting in 8-Bit Data Mode .............................. 135 Transmitting in 9-Bit Data Mode .............................. 135
W
Watchdog Timer Deep Sleep (DSWDT) ............................................. 171 Watchdog Timer (WDT) ................................................... 170 Windowed Operation ............................................... 170 WWW Address ................................................................ 218 WWW, On-Line Support ...................................................... 5
(c) 2009 Microchip Technology Inc.
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NOTES:
DS39937B-page 218
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(c) 2009 Microchip Technology Inc.
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39937B FAX: (______) _________ - _________
Device: PIC24F04KA201 Family Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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(c) 2009 Microchip Technology Inc.
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 04 KA2 01 T - I / SS - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Examples:
a) PIC24F04KA201-I/MQ: General purpose, 16-Kbyte program memory, 20-pin, Industrial temp., QFN package.
Architecture Flash Memory Family Product Group Pin Count
24 F
= 16-bit modified Harvard without DSP = Flash program memory
KA2 = General purpose microcontrollers 00 01 I P SL SO SS MQ ST = 14-pin = 20-pin = -40C to +85C (Industrial) = = = = = = PDIP SOIC, Narrow SOIC SSOP QFN TSSOP
Temperature Range Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
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Preliminary
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WORLDWIDE SALES AND SERVICE
AMERICAS
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03/26/09
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(c) 2009 Microchip Technology Inc.

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